ADE9178 datasheet(36/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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Rev. A | 36 of 122

Table 15. Calibration Registers Clamp Values

Feature

Registers1

Range (Register Values)

Range(Real Units)

Channel Gain

xVGAIN, xIGAIN, and AUXyGAIN

−402653184 to 134217728

±2 (Gain)

Channel Offset

xVOS, xIOS, and AUXyOS

±8388608

±8388608 (Codes)

RMS Offset

xVRMSOS, xIRMSOS, AUXyRMSOS,

xVRMSONEOS, xIRMSONEOS,

AUXyRMSONEOS, xVRMSHALFOS,

xIRMSHALFOS, AUXyRMSHALFOS,

ISUMRMSOS, VSUMRMSONEOS, and

VxyRMSONEOS

±2147483648

±2147483648 (Codes). For more details,

see the Root Mean Square (RMS)

Measurement section.

Power Gain

xPGAIN

−402653184 to 134217728

±2 (Gain)

Power Offset

xWATTOS

±134217728

±134217728 (Codes)

Phase Calibration

xVPHCAL, xIPHCAL, AUXy, and PHCAL ±134217728

±4.5 degrees at 50 Hz,

±5.4 degrees at 60 Hz

1 Where, x = A, B, or C, y = 0, 1, 2, 3, 4, or 5, and xy = AB, BC, and AC.

High-Pass Filter (HPF)

The HPF is provided on all the channels to remove DC offsets

for accurate RMS and energy measurements. It is enabled by

default with a corner frequency is 0.625 Hz. To disable the HPF, set

the HPFDIS bit in the CONFIG0 register. The corner frequency is

configured with the HPF_CRN bits in the CONFIG0 register.

Table 16. HPF Corner Gain with 50 Hz Input Signal

HPF_CRN1

f−3 dB Hz

HPF_GAIN

Settling Time to 1% for DC

Step (sec)

Settling Time to 0.1% for DC

Step (Sec)

38.7

0.797027686

0.0178

0.0268

19.6

0.940985831

0.0363

0.0544

9.90

0.987253714

0.0731

0.1097

4.97

0.997976919

0.1468

0.2202

2.49

0.999733627

0.2942

0.4412

1.25

0.999685117

0.5889

0.8833

6 (Default)

0.625

0.999428699

1.1784

1.7675

0.313

0.99924257

2.3573

3.5359

1 It is recommended to leave HPF_CRN as default. If HPF_CRN is changed, then a recalibration is required.

Phase Compensation

xPHCAL register is provided to compensate phase errors. By

default, all channels are delayed by one sample (4.5°). It is recom-

mended to keep the voltage channel xVPHCAL as default value

(0) to keep angle between voltages of different phases same. Use

the Equation 19 to calculate the xPHCAL value for a given phase

correction (ϕ)° angle for current with respect to its voltage.

xPHCAL

=sinϕ−ω+sinω

sin2ω−ϕ

×227,

wℎere

, ω=2π×fLINE× 14000

(19)

Zero Crossing and RMS Source Selection

The output of common processing block goes to feature calcula-

tions. As shown in Figure 49, additional bits are provided to choose

the sources to the following inputs:

►

One-Cycle RMS Input: RMSONE_SRC_SEL bit of CONFIG0

or after HPF.

►

Half-cycle RMS Input: RMSHALF_SRC_SEL bit of CONFIG0

or after HPF.

►

Zero-Crossing Input: ZX_SRC_SEL bit of CONFIG0 register

selects whether data used in the zero-crossing detection comes

before HPF or after phase compensation.

►

Phase Compensation Output: This goes to power and energy

calculations.

Note that the bits RMS_ONE_SRC_SEL, RMS_HALF_SRC_SEL,

ZX_SRC_SEL, and HPFDIS are common for all channels.

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