ADE9178 datasheet(23/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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Rev. A | 23 of 122

Table 7. ADC Channel to ADE9178 SLOT Mapping for Four and Three ADC Configurations

Four ADE9113/ADE9103s Connected

(ADC_CONFIG:NUM_ADC = 0x4)

Three ADE9113/ADE9103s Connected

(ADC_CONFIG:NUM_ADC = 0x3)

Four ADE9112s Connected (ADC_CONFIG:NUM_ADC

= 0x4)

Phase

ADC Channel

ADE9178 SLOT Phase

ADC Channel

ADE9178 SLOT Phase

ADC Channel

ADE9178 SLOT

SLOT0

SLOT1

SLOT2

N/A1

SLOT2

SLOT3

SLOT4

SLOT5

N/A1

SLOT5

SLOT6

SLOT7

SLOT8

N/A1

SLOT8

SLOT9

Not present

N/A1

SLOT9

SLOT10

Not present

N/A1

SLOT10

SLOT11

Not present

N/A1

SLOT11

N/A1

SLOT11

1 N/A means not applicable.

Note that this means for a change in NUM_ADC value away

from default (0x4) the ADC_REDIRECT0 and ADC_REDIRECT1

registers must be updated. For example, with a three ADE91xx

configuration shown in Figure 31, SLOT0 is now mapped to the

current channel of phase C rather than the current channel of

phase N.

For two channel ADCs (ADE9112), the V2 input is not present

therefore the V2 data is 0 in the data packet. For the four ADE9112

example shown in Table 7, the ADC_REDIRECT0 and ADC_RE-

DIRECT1 values stay the same as the four ADE9113/ADE9103

example except the data in SLOT2, SLOT5, SLOT8, and SLOT11 is

Table 8 shows the default values to write to ADC_REDIRECT0

and ADC_REDIRECT1 for different NUM_ADC values assuming

that the phase sequence matches the examples shown in Table 7

(ADE9178 MOSI connected to the first ADE91xx in the chain and

ADE9178 MISO connected to the last ADE91xx in the chain).

For channels that are not present, a slot number of 0x1F should

be written to corresponding bitfields of the ADC_REDIRECT0 and

ADC_REDIRECT1.

Table 8. Default ADC_REDIRECTx Values

NUM_ADC Value

ADC_REDIRECT0 Value ADC_REDIRECT1 Value

0x4

0x6431D2A

0x410150B

0x3

0x1190C7

0x3FFF88A8

0x2

0x3FF00464

0x3FFFFC45

0x1

0x3FFFFC01

0x3FFFFFE2

By default, for above connection, following mapping is done where

AV1, BV1, and CV1 are mapped to AV, BV, and CV and AV2, BV2,

CV2, NI, NV1, and NV2 are mapped to auxiliary channels as shown

in Figure 32.

Figure 32. ADC to ADE9178 Channel Mapping

Note that setting ADC_CONTROL RUN bit to 1 sets the sampling

rate of the ADCs to 4 kHz.

Multiple ADC Synchronization

If multiple ADCs are connected to ADE9178, the application can

periodically issue synchronization of these ADCs through the

ADC_CONTROL register. This ensures that all ADCs sample at

the same time. The ADC_CONTROL register can be used to

synchronize all ADCs periodically. To ensure correct operation, it

is recommended to synchronize ADCs by writing ADC_CONTROL

= 0x5 (ADC_SYNC = 1, ADC_RUN = 1) once every day. The

ADE9178 performs a synchronization sequence if the ADCs are out

of synchronization. Note that energy calculation can be disrupted

for ~1 ms during synchronization if it is required.

ADC SPI Protocol CRC

The ADE9178 checks whether there are any CRC errors in the data

transmitted by ADC over SPI. If there is a CRC error in the data

frame transmitted by an ADC, previous correct sample is used for

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