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ADE9178 数据表(PDF) 47 Page - Analog Devices

部件名 ADE9178
功能描述  Energy Management DSP with PEN Fault Detection
PDF  122 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE9178 数据表(HTML) 47 Page - Analog Devices

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Data Sheet
ADE9178
THEORY OF OPERATION
analog.com
Rev. A | 47 of 122
Figure 67. 4-Wire WYE, 4-Wire Delta Phase-Sequence Error from a Phase
Voltage Dropping below ZXTHRSH with SEQ_CYC = 1
MEASUREMENTS ONLY FOR CURRENT
CHANNELS
Neutral Current Mismatch
The ADE9178 calculates the RMS of the sum of AI + BI + CI sam-
ple by sample and stores the result in the ISUMRMS register. The
ISUMRMSOS register allows offset calibration of this measurement.
The scaling is the same as for the other xIRMS and xIRMSOS
registers. Additionally, any one of the six auxiliary ADC path can
be selected by configuring the ISUM_AUXSEL bits in CONFIG0
register to be used for neutral current sensing. This channel can
be either added or subtracted from the sum of phase channels by
configuring ISUM_CFG bits in CONFIG0 register.
In some cases, the application requires to get an interrupt if the
RMS of the sum of current channels exceeds a threshold. This
threshold value can be set in the ISUMLVL register.
ISUMMISMTCH bit of STATUS0 is set when ISUMRMS exceeds
ISUMLVL.
To calculate ISUMLVL, use the following formula:
ISUMLVL= INOMIFS ×
% of nominal ×
RMSFS_CODES
(36)
where, INOM is the nominal current, IFS is the current that gives
full scale at the ADC current input (system specific), % of nominal
is the required percentage of nominal for ISUMLVL, and RMSFS_CO-
DES is the RMS output value when full-scale input is applied to the
ADC input.
For example, if INOM is 10 A, IFS is 44.188 A, and the required
ISUMLVL is 5% of INOM, ISUMLVL is calculated as:
ISUMLVL= 1044.188 × 0.05 × 107310840
=1214253
 decimal=0x12872D
PEN FAULT DETECTION
This feature is designed to detect PEN faults according to the
BS7671:2018 Amendment 1:2020 standard.
The ADE9178 provides additional RMSONE calculation and dip/
swell detection on certain channels to enable easy PEN fault
detection. 3-channels are used for PEN fault detection, PEN_CHA-
NA, PEN_CHANB, and PEN_CHANC. The PEN channels can
be configured using the PEN_CHANSELA, PEN_CHANSELB, and
PEN_CHANSELC bits in the PEN_CONFIG register. The PEN
channels can be any of the 12 ADC channels AV, BV, CV,
AI, BI, CI, AUX0, AUX1, AUX2, AUX3, AUX4, and AUX5. CON-
FIG0:RMSONE_SRC_SEL selects samples either before or after
the HPF.
RMS of PEN Fault Channels
Four additional one-cycle RMS values (same as RMS of One Cycle
section) are calculated on the following signals:
1. VSUMRMSONE = (PEN_CHANA + PEN_CHANB +
PEN_CHANC)/3
2. VABRMSONE = PEN_CHANA − PEN_CHANB
3. VACRMSONE = PEN_CHANA − PEN_CHANC
4. VBCRMSONE = PEN_CHANB − PEN_CHANC
RMSONE_SRC_SEL bit in the CONFIG0 register decides and se-
lects samples either before or after the HPF. Period is calculated for
any one of the selected PEN channels based on PEN_LP_SEL bits
in the PEN_CONFIG and is stored in the PEN_PERIOD register
(for formula to convert to seconds, see Table 14). This period value
is used for the PEN channel RMS measurements. Separate RMS
offset calibration registers are also provided for each of PEN chan-
nel (VSUMRMSONEOS, VABRMSONEOS, VACRMSONEOS, and
VBCRMSONEOS). The PEN channel RMS offset register format is
the same as the other RMS offset registers (xxRMSOS).
For example, if PEN_CONFIG is set up in the following configura-
tion:
PEN_CHANSELA = 0000 = AV data processing path
PEN_CHANSELB = 0010 = BV data processing path
PEN_CHANSELC = 0100 = CV data processing path
PEN_LP_SEL = 11 = Combined PEN channels (AV + BV − CV)/2
Then the PEN fault output registers is calculated as follows:
VSUMRMSONE = (AV + BV + CV)/3
VABRMSONE = AV − BV
VACRMSONE = AV − CV
VBCRMSONE = BV − CV
PEN_PERIOD = Period of combined PEN channels
Dips and Swells on PEN Fault Channels
Swells can be detected based on VSUMRMSONE value while both
dips and swells can be detected on the 3-phase to phase voltage
RMS values (VABRMSONE, VACRMSONE, and VBCRMSONE).
Separate dip/swell levels and cycle configuration registers (VxxDI-



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