ADE9178 datasheet(37/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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Rev. A | 37 of 122

POWER AND ENERGY MEASUREMENTS

Power Calculation

Total Active Power

The ADE9178 computes total active power on up to 3-phases. The

measurement is equal to the sum of active power of all fundamental

and harmonic components of the voltages and currents.

The total active power on each phase is calculated by first mul-

tiplying the xI_PCF and xV_PCF waveforms. Then the result is

low-pass filtered, unless the DISAPLPF bit in the CONFIG0 register

is equal to 1. Finally, the xPGAIN is applied to perform a gain

correction and the xWATTOS value is applied to correct the watt off-

set. The active power calculations, one for each channel (AWATT,

BWATT, and CWATT), are calculated internally at a 4 kHz rate but

the output registers are updated at a 1 kHz rate. The complete

datapath is shown in Figure 50.

Figure 50. Total Active Power Datapath

The low-pass filter (LPF), LPF2, extracts the total active power,

which attenuates harmonics of a 50 Hz or 60 Hz fundamental by

114 dB so that, at full scale, the variation in the low-pass filtered

active power is very small, ±0.0002%. Enable the LPF2 (DISAPLPF

= 0) for normal operation. Disable LPF2 (by setting DISAPLPF to 1)

in the CONFIG0 register to obtain instantaneous total active power.

DISAPLPF is 0 at reset.

Figure 51. LPF Diagram

The total active power measurements can be calibrated by gain

and offset. Equation 20 indicates how the gain and offset calibration

registers modify the results in the corresponding power registers:

xWATT

= 1+xPGAIN227 ×xWATT0

+xWATTOS

(20)

where, xWATT0 is the initial xWATT register value (decimal) before

gain and offset calibration. For the worked example, see the Power

Gain Calibration section.

The xWSIGN bits in the PHSIGN register indicate the sign of the

active power value. Bits [3:1] (REVAPC, REVAPB, and REVAPA)

in the STATUS0 register are set when a sign change occurs in the

active power measurement.

PWR_SETTLE[17:16] bits in the CONFIG0 register configure the

time for the power measurements to settle before starting the

energy and CF accumulators. Timer starts when ADC_RUN bit of

ADC_CONTROL register is set to 1, then waits the time configured

in PWR_SETTLE register, then starts power calculations.

Table 17. Total Active Power Settling Time for 50 Hz Input

Total Active Power Settling Time (Sec)

Configuration

FS = 99%

FS = 99.9%

HPF On, LPF2 On

1.0581

1.41304

HPF On, LPF2 Off

0.23525

0.79525

Total Apparent Power

The ADE9178 computes total apparent power on up to 3-phases.

Apparent power is calculated by multiplying the current RMS meas-

urement (xIRMS), by the corresponding voltage RMS (xVRMS),

and then applying a gain correction (xPGAIN). The result is stored

in the xVA register, which is calculated internally at a 4 kHz rate but

the output register is updated at a 1 kHz rate. Note that the offset

of the total apparent power calculation is performed by calibrating

the xIRMS and xVRMS measurements (using the xIRMSOS and

xVRMSOS registers), and there is no specific offset compensation

The ADE9178 offers a register (VNOM) that contains a default RMS

value. If the VNOMx_EN bits in the CONFIG0 register are set,

VNOM RMS is multiplied with xIRMS to calculate xVA.

To calculate VNOM register value, use the following formula:

VNOM=V×RMSFS_CODES

VFS_T

(21)

where, V is the required nominal voltage, RMSFS_CODES is the RMS

output value when full-scale input is applied to the ADC input, and

VFS_T is the voltage that gives full scale at the ADC voltage input

(system specific).

For example, if the required nominal voltage is 230 V and VFS_T is

707 V, VNOM is calculated as:

VNOM=230×107310840

707

34910174 decimal

0×214AFDE

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