ADE9178 datasheet(45/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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Rev. A | 45 of 122

Peak Detection

The ADE9178 records the peak value measured on the current,

voltage, and auxiliary channels, from the xPCF waveforms. The

VPEAKSEL[2:0], IPEAKSEL[2:0], and AUXPEAKSEL[5:0] bits in

the PEAK_CONFIG register allow the user to select which channels

to monitor for peak detection.

The IPEAK register stores the peak current value in IPEAKV-

AL[23:0] and indicates which phase(s) currents reached the value

in the IPPHASE[2:0] bits. Similarly, VPEAKVAL and VPPHASE

bits of VPEAK register and AUXPEAKVAL and AUXPHASE bits

in AUXPEAK registers provides similar information for voltage and

auxiliary channels, respectively.

Note that the range of the PEAK output is clamped to ±8388607

codes.

Dip and Swells

Dip indicates that if the RMS of input signal reaches below a speci-

fied threshold for a user-configured number of cycles. Conversely,

swell indicates that if the RMS of input signal reaches above a

threshold for a specified number of cycles. The ADE9178 supports

dip/swell detection on RMSONE and RMSHALF outputs for all ADC

channels.

The corresponding xRMSHALF or xRMSONE is compared against

the configured xDIPHALF_LVL or xDIPONE_LVL. If the consecutive

RMS values are less than the level for configured number of

xDIPHALF_CYC (register unit in half-line cycles) or xDIPONE_CYC

(register value units in one-line cycles), then the corresponding

smallest dip RMS value is updated in xDIPONE or xDIPHALF

registers (same register format as all RMS output registers). Each

channel is associated with separate LVL and CYC registers. For

example, if the application wants to flag DIP if the AVRMSONE

reaches below 20% of the full scale for five-line cycles, then AVDI-

PONE_LVL register must be configured as RMSFS_CODE × 0.2 =

107310840 × 0.2 = 21462168 decimal and AVDIPONE_CYC must

be set to 5 decimal. Note that if 0 or 1 is written to the CYC register,

the dip/swell flag is set after one cycle.

Similarly, for swell detection, corresponding xRMSHALF or

xRMSONE is compared against the configured xSWELLHALF_LVL

or xSWELLONE_LVL. If the consecutive RMS values are greater

than the level for configured number of xSWELLHALF_CYC or

xSWELLONE_CYC, then maximum RMS values is updated in the

xSWELLONE or xSWELLHALF registers. Each channel is associat-

ed with separate LVL and CYC registers.

Status of RMSONE dips/swells is provided in STATUS2 register

and status of RMSHALF dips/swells is provided in STATUS3 regis-

ter. If DIP_SWELL_x_IRQ_MODE bit in CONFIG0 register is set,

then bit in STATUS registers is set only when entering or exiting

the dip or swell condition. Otherwise by default, the bit is set

continuously after every xDIPx_CYC or xSWELLX_CYC cycles.

IRQ2/IRQ3 outputs can be enabled by setting the appropriate bit in

the MASK2/MASK3 registers to generate interrupts for these flags.

Figure 61 and Figure 62 show the expected behavior for both

continuous and enter and exit IRQ modes. In both examples, the

CYC register is set to 0x2.

Figure 61. Continuous IRQ Mode

Figure 62. Enter and Exit IRQ Mode

Angle Measurement

The ADE9178 measures angles between voltage signals, current

signals, and angle between voltage and current signals. Note that

angle measurement is not available for auxiliary channels. It is

measured as the time between negative to positive zero crossings

of corresponding signals as shown in Figure 63 and Figure 64.

Figure 63. Angle between Voltages

Figure 64. Angle between Voltage and Current

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