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Data Sheet

ADE9178

THEORY OF OPERATION

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Rev. A | 38 of 122

Note that the fully-differential VFS_T is used for this calculation. See

the Worked Examples section on how to calculate VFS_T for the

system.

The complete apparent power signal processing datapath is shown

in Figure 52.

Figure 52. Total Apparent Power Path

Table 18. Total Apparent Power Settling Time with 50 Hz Input

Total Apparent Power Settling Time (Sec)

Configuration

FS = 99%

FS = 99.9%

HPF On, LPF On

1.05754

1.41282

Energy Calculation

The energy path consists of an internal accumulator updating at

4 kHz rate, to perform summation of power outputs. The accumula-

tion is carried out for either a user-defined time duration or number

of half-line cycles based upon the EGY_TMR_MODE bit configured

in the EP_CFG register. It is recommended to use time-based accu-

mulation mode (for more details, see Table 30). The time or half-line

cycles is set in the EGY_TIME register. Set the EGY_PWR_EN bit

in EP_CFG register to enable energy accumulation.

After EGY_TIME + 1 ms or EGY_TIME + 1 half-line cycle (depend-

ing on EGY_TMR_MODE), the EGYRDY bit is set in the STATUS0

the time accumulation mode, four samples of power are produced

every 1 ms so the expected output codes in the energy register

for a full-scale input signal is POWFS_CODES × 4 × (EGY_TIME +

1). For line-cycle accumulation mode, the expected output codes

in the energy register for a full-scale input signal is POWFS_CODES

× 4 × (EGY_TIME + 1) × (half_line cycle/1 ms). This is due to

power being calculated internally at a 4 kHz rate. The data from the

internal energy accumulator is either added or latched to the output

EP_CFG register. The user can configure automatic resetting the

energy output register after reading them using the RD_RST_EN

bit in the EP_CFG register. Figure 53 shows an overview of

energy accumulation. Three separate accumulators are provided

for positive, negative, and signed accumulation. Even though the

Figure 53 shows only accumulation of AWATT, there are similar

separate accumulators for other active energy channels (BWATT

and CWATT). Apparent energy channels (AVA, BVA, and CVA) only

have positive accumulators. Energy is not accumulated if no load is

detected.

Figure 53. No Load and Sign Check

where, x is the phase (A, B, or C) and xxx is either ACT or APP,

which depends on if the calculated energy is active or apparent.

Figure 54. Energy Accumulation Flow

In half-line cycle accumulation mode, the energy is accumulated

over an integer number of half-line cycles and is synchronized to

one of the voltage channels zero crossings decided by the ZX_SEL

bits in the ZX_LP_SEL register. The advantage of summing the

active energy over an integer number of line cycles is that the

sinusoidal component in the active energy is reduced to 0. This

eliminates any ripple in the energy calculation and allows the ener-

gy to be accumulated accurately over a shorter time. This mode

greatly simplifies the energy calibration and significantly reduces

the time required to calibrate the meter.

Note that with full-scale inputs, the internal and output energy

registers overflows in 51.242 sec of samples. Hence, EGY_TIME

cycle accumulation and lower than 51241d in time accumulation

mode to prevent overflowing of the output registers.

Each energy output register is 45-bits wide, split between two

registers: a register containing the 32 MSB, xHR_xx_HI or xHR_HI ,

and a register containing the 13 LSB, xHR_xx_LO or xHR_LO

(where, x = xWATT or xVA and xx = SIGNED, POS or NEG, for

example, AWATTHR_POS_HI or AVAHR_HI). The lower 13 bits of

energy output are stored in the xHR_LO register.

For example, if the accumulated energy value is

0x0456789ABCDE, then xHR_xx_HI or xHR_HI stores

0x22B3C4D5 and xHR_xx_LO or xHR_LO stores 0x1CDE.

In some installations, it is not required to accumulate energy at

very high precision. In such cases, only the xHR_xx_HI or xHR_HI

XHR_LO register.

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