ADE9178 datasheet(57/122 Pages) AD

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Data Sheet

ADE9178

APPLICATIONS INFORMATION

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Rev. A | 57 of 122

Example

If APFMEASURED = 67144872 decimal, then:

ϕ= π3−cos−1 67144872227 ×−1=−0

.00031

(60)

For 50 Hz signal:

ω=2π×50× 14000=0.07854

(61)

AIPHCAL=sin−0.00031−0.07854+sin0.07854

sin2×0.07854−−0.00031

×227=

−264472 decimal=0×FFFBF6E8 (62)

QUICK START

This section describes how to setup the ADE9178 and ADE91xx

chipset for a 3-phase and 4-wire measurement. To setup, do the

following steps:

1. Configure the Host MCU to monitor to IRQ0, IRQ1,

HOST_RDY, and HOST_ERR pins of the ADE9178.

2. Issue a hardware reset to ADE9178 and ADCs by toggling

corresponding reset pins. For more details, see the Hardware

Reset section.

3. The ADE9178 checks the integrity during boot time and both

HOST_RDY and HOST_ERR pins go low if the integrity error is

detected. If this happens, then toggle the hardware reset pin of

the ADE9178. If the error persists, contact support team.

4. Wait for IRQ0 interrupt from the ADE9178 and:

a. Read the STATUS0 register and check that the RSTDONE

bit is set. Note that once the hardware reset is initiated, it

takes 16 ms before IRQ0 is asserted. Otherwise, there is an

internal error and it is recommended to reset the ADE9178.

b. Clear RSTDONE interrupt by writing 1 to the RSTDONE bit

in the STATUS0 register.

5. By default all error interrupts in the ERROR_STATUS register

are enabled and IRQ1 is triggered if there is an error. The de-

tails of the error can be obtained by reading ERROR_STATUS

section.

6. If energy is monitored using the CF outputs, configure the

following registers (skip this step if the CF outputs are not

used):

a. Configure the PWRSEL bits in the CFx_CONFIG register to

select the energy type to monitor.

b. Configure the PHASESEL bits in the CFx_CONFIG register

to select the phases to include in the CF calculation.

c. Configure the ACCMODE bits in the CFx_CONFIG register

to select the accumulation mode.

d. Set the CFx_THR register based on the required impulses

per kilowatt-hour. For CFx_THR formula, see the CF Pulse

Generation section.

e. Configure the WIDTHSEL bit in the CFx_CONFIG register

to set the low-pulse width. For more details, see Table 20.

f. Enable the CF by clearing the CFDIS bit in the CFx_CON-

FIG register to 0.

7. If energy is monitored using energy registers, configure the

following registers:

a. Configure the EGY_TMR_MODE bit in the EP_CFG

(EGY_TMR_MODE = 0). Set the required samples in the

EGY_TIME register (N − 1 ms).

1. It is recommended to use time-based accumulation

mode (for more details, see Table 30).

b. Configure the EGY_LD_ACCUM bit in the EP_CFG register

to add the internal energy register to user energy register

on EGYRDY (EGY_LD_ACCUM = 0), or to overwrite the

user energy register with the internal energy register value

(EGY_LD_ACCUM = 1).

c. Configure the RD_RST_EN bit in the EP_CFG register to

enable reset of user energy registers on read (RD_RST_EN

= 1), or to disable reset of user energy registers on read

(RD_RST_EN = 0).

d. Configure the NOLOAD_TMR bits in the EP_CFG register

and set the ACT_NL_LVL and APP_NL_LVL level registers

to detect no load and prevent energy accumulation of noise.

For more details, see the No Load Detection section.

8. The ADE9178 can provide interrupts for a variety of events on

the IRQ0, IRQ1, IRQ2, and IRQ3 pins. The MASK0, MASK1,

MASK2, MASK3, or ERROR_MASK and STATUS0, STATUS1,

STATUS2, STATUS3, or ERROR_STATUS registers manage

the respective interrupt pins. For more details, see the Inter-

rupts and Status Outputs section.

9. Write calibration coefficient registers to the ADE9178. For more

details, see the Calibration Method section.

10. Configure ADC related parameters and start the data process-

ing as follows:

a. Configure number of ADCs connected by writing to the

NUM_ADC bits in the ADC_CONFIG register.

b. Review ADC_REDIRECT1 and ADC_REDIRECT2 default

values and update if the channel mapping required is

different to default. Note that the ADC_REDIRECT1 and

ADC_REDIRECT2 must be updated if the number of ADCs

present is different than the default 4. For more details, see

Table 8.

c. Initialize the ADCs by setting ADC_INIT bit in the

ADC_CONTROL register to 1 (Auto Clears).

d. Separately, enable data capture and processing by setting

the ADC_RUN bit in the ADC_CONTROL register to 1

(Auto Clears is setting ADC_RUN = 1 fails).

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