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ADE9178 数据表(PDF) 87 Page - Analog Devices

部件名 ADE9178
功能描述  Energy Management DSP with PEN Fault Detection
PDF  122 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE9178 数据表(HTML) 87 Page - Analog Devices

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Data Sheet
ADE9178
REGISTER DETAILS: ADE9178
analog.com
Rev. A | 87 of 122
Table 34. ADE9178 Register Details (Continued)
Addr
Name
Bits
Bit Name
Settings
Description
Reset
Access
11
CRC_SWELLONE_CYC_EN
CRC SWELLONE_CYC
Enable. Set this bit to
include the xSWELLONE_CYC
registers of all ADC channels in
the configuration register CRC
calculation.
0x0
R/W
10
CRC_SWELLONE_LVL_EN
CRC SWELLONE_LVL Enable.
Set this bit to include the
xSWELLONE_LVL registers of
all ADC channels in the
configuration register CRC
calculation.
0x0
R/W
9
CRC_SWELLHALF_CYC_EN
CRC SWELLHALF_CYC
Enable. Set this bit to include
the xSWELLHALF_CYC
registers of all ADC channels in
the configuration register CRC
calculation.
0x0
R/W
8
CRC_SWELLHALF_LVL_EN
CRC SWELLHALF_LVL
Enable. Set this bit to
include the xSWELLHALF_LVL
registers of all ADC channels in
the configuration register CRC
calculation.
0x0
R/W
7
CRC_DIPONE_CYC_EN
CRC DIPONE_CYC Enable.
Set this bit to include the
xDIPONE_CYC registers of
all ADC channels in the
configuration register CRC
calculation.
0x0
R/W
6
CRC_DIPONE_LVL_EN
CRC DIPONE_LVL Enable.
Set this bit to include the
xDIPONE_LVL registers of
all ADC channels in the
configuration register CRC
calculation.
0x0
R/W
5
CRC_DIPHALF_CYC_EN
CRC DIPHALF_CYC Enable.
Set this bit to include the
xDIPHALF_CYC registers of
all ADC channels in the
configuration register CRC
calculation.
0x0
R/W
4
CRC_DIPHALF_LVL_EN
CRC DIPHALF_LVL Enable.
Set this bit to include the
xDIPHALF_LVL registers of
all ADC channels in the
configuration register CRC
calculation.
0x0
R/W
3
CRC_MASK3_EN
CRC MASK3 Enable. Set this
bit to include the MASK3
register in the configuration
register CRC calculation.
0x0
R/W
2
CRC_MASK2_EN
CRC MASK2 Enable. Set this
bit to include the MASK2
0x0
R/W



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