ADE9178 datasheet(49/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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Rev. A | 49 of 122

OUTPUT REGISTER UPDATE RATES

Most of the ADE9178 output registers are updated every 1 ms interval (1 kHz rate). Table 26 summarizes the list of registers that are not

updated at the 1 kHz rate.

Table 26. Update Rates

Description

Update Rate

Status Bits

xxRMSONE

One-cycle RMS registers

Line period

RMSONERDY (STATUS0/1)

xxRMSHALF

Half-cycle RMS registers

2 × line period

ZXxx(STATUS0/1)

xWATTHR_POS_LO/HI,

xWATTHR_NEG_LO/HI,

xWATTHR_SIGNED_LO/HI xVAHR_LO/HI

Active/apparent energy registers

Depends on EGY_TMR_MODE bit of

EP_CFG

EGYRDY (STATUS0/1)

xPF

Power factor

1 Hz

PF_RDY (STATUS0/1)

xxDIPHALF

Minimum RMSHALF during a half-cycle

dip event

2 × line period, but updated only when

DIPHALF is detected

xxDIPHALF (STATUS3)

xxDIPONE

Minimum RMSONE during a one-cycle

dip event

Line period but updated only when

DIPONE is detected

xxDIPONE (STATUS2)

xxSWELLHALF

Maximum RMSHALF during a half-

cycle swell event

2 × line period, but updated only when

SWELLHALF is detected

xxSWELLHALF (STATUS3)

xxSWELLONE

Maximum RMSONE during a one-cycle

swell event

Line period but updated only when

SWELLONE is detected

xxSWELLONE (STATUS2)

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