ADE9178 datasheet(78/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 78 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

0111

AUX1 Data Processing Path.

1000

AUX2 Data Processing Path.

1001

AUX3 Data Processing Path.

1010

AUX4 Data Processing Path.

1011

AUX5 Data Processing Path.

0x0B1

CF1_CONFIG

[31:11]

RESERVED

Reserved.

0x0

ACC_CLEAR

Clear CF1 Accumulator.

Set this bit to clear the

accumulation in the digital to

frequency converter. Note that

this bit automatically clears

itself.

0x0

R/W

WIDTHSEL

CF1 Pulse Width Select. If this

bit is set, the CF1 pulse width

is determined by the CF_LTMR

equal to zero, the active-low

pulse width is set at 80 ms

for frequencies lower than 6.25

Hz.

0x0

R/W

[8:7]

ACCMODE

CF1 Accumulation Mode

Configuration.

0x0

R/W

Signed Accumulation Mode.

Positive Accumulation Mode.

Negative Accumulation Mode.

[6:4]

PHASESEL

Phases to Include in CF1

Pulse Output. PHASESEL[0]

set to 1 to include phase

A in the CF1 outputs

calculations. PHASESEL[1] set

to 1 to include phase B in

the CF1 outputs calculations.

PHASESEL[2] set to 1 to

include phase C in the CF1

outputs calculations.

0x0

R/W

[3:1]

PWRSEL

CF1 Energy Output Type. Type

of energy output on the CF1

pin. Configure PHASESEL1

in the CF1_CONFIG register

to select which phases are

included.

0x0

R/W

000

Total Active Power.

001

Total Apparent Power.

CFDIS

CF1 Output Disable. Set this bit

to disable the CF1 output and

bring the pin high. Note that

when this bit is set, the CF1 bit

in STATUS0 is not set when a

CF pulse is accumulated in the

digital to frequency converter.

0x1

R/W

0x0B2

CF2_CONFIG

[31:11]

RESERVED

Reserved.

0x0

ACC_CLEAR

Clear CF2 Accumulator.

Set this bit to clear the

accumulation in the digital to

0x0

R/W

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