ADE9178 datasheet(74/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 74 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

Continuous Interrupts. Get

continuous interrupts after

every DIP_CYC/SWELL_CYC

cycles.

Enter and Exit Interrupts. Get

one interrupt when entering

DIP/SWELL mode and another

interrupt when exiting DIP/

SWELL mode.

DIP_SWELL_HALF_IRQ_MODE

Dip and Swell Half-Cycle

Interrupt Mode Selection.

0x0

R/W

Continuous Interrupts. Get

continuous interrupts after

every DIP_CYC/SWELL_CYC

cycles.

Enter and Exit Interrupts. Get

one interrupt when entering

DIP/SWELL mode and another

interrupt when exiting DIP/

SWELL mode.

[17:16]

PWR_SETTLE

Power Settling Time Selection.

These bits configure the time

for the power measurements

to settle before starting the

energy and CF accumulations.

0x0

R/W

Settle for 64 ms.

Settle for 128 ms.

Settle for 256 ms.

Settle for 0 ms.

VNOMC_EN

Nominal Phase Voltage RMS

for Phase C Total Apparent

Power. Set this bit to use the

nominal phase voltage RMS,

VNOM, in the computation of

Phase C total apparent power,

CVA.

0x0

R/W

VNOMB_EN

Nominal Phase Voltage RMS

for Phase B Total Apparent

Power. Set this bit to use the

nominal phase voltage RMS,

VNOM, in the computation of

Phase B total apparent power,

BVA.

0x0

R/W

VNOMA_EN

Nominal Phase Voltage RMS

for Phase A Total Apparent

Power. Set this bit to use the

nominal phase voltage RMS,

VNOM, in the computation of

Phase A total apparent power,

AVA.

0x0

R/W

ZX_SRC_SEL

Zero-Crossing Source Select.

This bit selects whether data

going into the zero-crossing

detection circuit comes before

the HPF or after the PCF.

0x0

R/W

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