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ADE9178 数据表(PDF) 93 Page - Analog Devices |
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ADE9178 数据表(HTML) 93 Page - Analog Devices |
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93 / 122 page  Data Sheet ADE9178 REGISTER DETAILS: ADE9178 analog.com Rev. A | 93 of 122 Table 34. ADE9178 Register Details (Continued) Addr Name Bits Bit Name Settings Description Reset Access timeout on phase B. This means that a zero crossing on the phase B voltage is missing. 16 ZXTOAV Phase A Voltage Zero-Crossing Timeout. This bit is set to indicate a zero-crossing timeout on phase A. This means that a zero crossing on the Phase A voltage is missing. 0x0 R/W1C 15 SEQERR Phase Sequence Error Occurred on Voltage Zero Crossings. This bit is set if zero crossings on three voltage phases does not follow phase A − phase B − phase C sequence. 0x0 R/W1C 14 RSTDONE Reset Completed and Ready for SPI Communication. This bit is set to indicate that reset is complete and board is ready for SPI communication. 0x0 R/W1C 13 CRC_CHG CRC Changed. This bit is set if any of the registers monitored by the configuration register CRC change value. The CRC_RSLT register holds the new configuration register CRC value. 0x0 R/W1C 12 VANLOAD Total Apparent Energy No Load Condition Changed. This bit is set when one or more phase of total apparent energy enters or exits the no load condition. 0x0 R/W1C 11 WATTNLOAD Total Active Energy No Load Condition Changed. This bit is set when one or more phase of total active energy enters or exits the no load condition. 0x0 R/W1C 10 ISUMMISMTCH ISUM RMS Mismatch. This bit is set to indicate a change in the relationship between ISUMRMS and ISUMLVL. 0x0 R/W1C 9 PF_RDY Power Factor Data Ready. This bit is set to indicate that power factor measurements are updated, every 1 sec. 0x0 R/W1C 8 RMSONERDY One-Cycle RMS Data Ready. This bit is set when the one- cycle RMS values are updated. 0x0 R/W1C 7 CF2 CF2 Pulse Issued. This bit is set when a CF2 pulse is issued, when the CF2 pin goes from a high to low state. 0x0 R/W1C 6 CF1 CF1 Pulse Issued. This bit is set when a CF1 pulse is 0x0 R/W1C |
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