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ADE9178 数据表(PDF) 60 Page - Analog Devices |
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ADE9178 数据表(HTML) 60 Page - Analog Devices |
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60 / 122 page  Data Sheet ADE9178 REGISTER NUMBER FORMAT analog.com Rev. A | 60 of 122 Table 31 shows if the number is signed/unsigned and specifies the valid range for input registers. Table 31. Register Number Format Register Group Relevant Registers Input/Output Register Signed/Unsigned Range Related Section Gain Registers xxGAIN, AUXyGAIN Input Signed 0xE8000000 to 0x8000000 Gain Calibration, Power Gain Calibration Phase Cal Registers xxPHCAL, AUXyPHCAL Input Signed 0xF8000000 to 0x8000000 Phase Calibration Active Power Offset Registers xWATTOS Input Signed 0xF8000000 to 0x8000000 Power Offset Calibration No Load Level Registers xxx_NL_LVL Input Unsigned 0x0 to 0x7FFFFFFF No Load Detection Channel Offset Registers xxOS, AUXyOS Input Signed 0xFF800000 to 0x800000 Gain and Offset Compensation RMS Offset Registers xxRMSOS, xxRMSHALFOS, xxRMSONEOS, AUXyRMSOS, AUXyRMSHALFOS, AUXyRMSONEOS, ISUMRMSOS, VSUMRMSONEOS, VxxRMSONEOS Input Signed 0x80000000 to 0x7FFFFFFF RMS Offset Calibration CF Threshold CF1_THR, CF2_THR Input Unsigned 0x28ED2D to 0x7FFFFFFF CF Pulse Generation Dip/Swell Cycle Registers xxDIPHALF_CYC, xxDIPONE_CYC, AUXyDIPHALF_CYC, AUXyDIPONE_CYC, xxSWELLHALF_CYC, xxSWELLONE_CYC, AUXySWELLHALF_CYC, AUXySWELLONE_CYC, VSUMSWELLONE_CYC, VxxDIPONE_CYC, VxxSWELLONE_CYC Input Unsigned 0x0 to 0xFFFFFFFF Dip and Swells Zero-Crossing Timeout ZXTOUT Input Unsigned 0x0 to 0xFFFFFFFF Zero-Crossing Timeout Phase-Sequence Error Detection SEQ_CYC Input Unsigned 0x0 to 0xFFFFFFFF Phase-Sequence Error Detection Energy Accumulation Time EGY_TIME Input Unsigned 0x0 to 0xFFFFFFFF Energy Calculation CF Pulse-Width Configuration CF_LTMR Input Unsigned 0x1 to 0x13880 CF Pulse Generation Zero-Crossing Threshold ZXTHRSH Input Unsigned 0x0 to 0xFFFFFFFF Zero-Crossing Detection User-Configured Period Values USER_PERIOD, USER_PERIOD_HALF Input Unsigned 0x0 to 0xFFFFFFFF RMS of One Cycle, RMS of Half Cycle Dip/Swell Level Registers xxDIPHALF_LVL, xxDIPONE_LVL, AUXyDIPHALF_LVL, AUXyDIPONE_LVL, xxSWELLHALF_LVL, xxSWELLONE_LVL, AUXySWELLHALF_LVL, AUXySWELLONE_LVL, VSUMSWELLONE_LVL, VxxDIPONE_LVL, VxxSWELLONE_LVL Input Unsigned 0x0 to 0xFFFFFFFF Dip and Swells ISUMRMS Threshold ISUMLVL Input Unsigned 0x0 to 0xFFFFFFFF Neutral Current Mismatch |
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