ADE9178 datasheet(79/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 79 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

frequency converter. Note that

this bit automatically clears

itself.

WIDTHSEL

CF2 Pulse Width Select. If this

bit is set, the CF2 pulse width

is determined by the CF_LTMR

equal to zero, the active-low

pulse width is set at 80 ms

for frequencies lower than 6.25

Hz.

0x0

R/W

[8:7]

ACCMODE

CF2 Accumulation Mode

Configuration.

0x0

R/W

Signed Accumulation Mode.

Positive Accumulation Mode.

Negative Accumulation Mode.

[6:4]

PHASESEL

Phases to Include in CF2

Pulse Output. PHASESEL[0]

set to 1 to include phase

A in the CF2 outputs

calculations. PHASESEL[1] set

to 1 to include phase B in

the CF2 outputs calculations.

PHASESEL[2] set to 1 to

include phase C in the CF2

outputs calculations.

0x0

R/W

[3:1]

PWRSEL

CF2 Energy Output Type. Type

of energy output on the CF2

pin. Configure PHASESEL2

in the CF2_CONFIG register

to select which phases are

included.

0x0

R/W

000

Total Active Power.

001

Total Apparent Power.

CFDIS

CF2 Output Disable. Set this bit

to disable the CF2 output and

bring the pin high. Note that

when this bit is set, the CF2 bit

in STATUS0 is not set when a

CF pulse is accumulated in the

digital to frequency converter.

0x1

R/W

0x0B7

RMSHALF_CONFIG

[31:12]

RESERVED

Reserved.

0x0

AUX5_RMSHALF_MODE_SEL

AUX5RMSHALF Mode

Selection. Set this

bit to calculate

AUX5RMSHALF based on

USER_PERIOD_HALF or

else synchronize with zero

crossings of AUX5 channel.

0x0

R/W

Synchronized with Zero

Crossing. Synchronize

RMSHALF calculation with

zero crossings of the channel.

Synchronized with User-

Defined Half Period Value.

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