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CY8CKIT-059 数据表(PDF) 23 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 23 Page - Infineon Technologies AG |
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23 / 140 page  Document Number: 001-84932 Rev. *N Page 22 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 5.7 Memory Map The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.7.1 Address Map The 4-GB address space is divided into the ranges shown in Table 5-4: The bit-band feature allows individual bits in SRAM to be read or written as atomic operations. This is done by reading or writing bit 0 of corresponding words in the bit-band alias region. For example, to set bit 3 in the word at address 0x20000000, write a 1 to address 0x2200000C. To test the value of that bit, read address 0x2200000C and the result is either 0 or 1 depending on the value of the bit. Most memory accesses done by the Cortex-M3 are aligned, that is, done on word (4-byte) boundary addresses. Unaligned accesses of words and 16-bit half-words on nonword boundary addresses can also be done, although they are less efficient. 5.7.2 Address Map and Cortex-M3 Buses The ICode and DCode buses are used only for accesses within the Code address range, 0–0x1FFFFFFF. The System bus is used for data accesses and debug accesses within the ranges 0x20000000–0xDFFFFFFF and 0xE0100000–0xFFFFFFFF. Instruction fetches can also be done within the range 0x20000000–0x3FFFFFFF, although these can be slower than instruction fetches via the ICode bus. The private peripheral bus (PPB) is used within the Cortex-M3 to access system control registers and debug and trace module registers. Table 5-4. Address Map Address Range Size Use 0x00000000– 0x1FFFFFFF 0.5 GB Program code. This includes the exception vector table at power up, which starts at address 0. 0x20000000– 0x3FFFFFFF 0.5 GB Static RAM. This includes a 1 MByte bit-band region starting at 0x20000000 and a 32 Mbyte bit-band alias region starting at 0x22000000. 0x40000000– 0x5FFFFFFF 0.5 GB Peripherals. 0x60000000– 0x9FFFFFFF 1 GB External RAM. 0xA0000000– 0xDFFFFFFF 1 GB External peripherals. 0xE0000000– 0xFFFFFFFF 0.5 GB Internal peripherals, including the NVIC and debug and trace modules. Table 5-5. Peripheral Data Address Map Address Range Purpose 0x00000000–0x0003FFFF 256 KB flash 0x1FFF8000–0x1FFFFFFF 32 KB SRAM in Code region 0x20000000–0x20007FFF 32 KB SRAM in SRAM region 0x40004000–0x400042FF Clocking, PLLs, and oscillators 0x40004300–0x400043FF Power management 0x40004500–0x400045FF Ports interrupt control 0x40004700–0x400047FF Flash programming interface 0x40004800–0x400048FF Cache controller 0x40004900–0x400049FF I2C controller 0x40004E00–0x40004EFF Decimator 0x40004F00–0x40004FFF Fixed timer/counter/PWMs 0x40005000–0x400051FF I/O ports control 0x40005400–0x400054FF External Memory Interface (EMIF) control registers 0x40005800–0x40005FFF Analog Subsystem Interface 0x40006000–0x400060FF USB Controller 0x40006400–0x40006FFF UDB Working Registers 0x40007000–0x40007FFF PHUB Configuration 0x40008000–0x400087FF EEPROM 0x4000A000–0x4000A400 CAN 0x4000C000–0x4000C800 Digital Filter Block 0x40010000–0x4001FFFF Digital Interconnect Configuration 0x48000000–0x48007FFF Flash ECC Bytes 0x60000000–0x60FFFFFF External Memory Interface (EMIF) 0xE0000000–0xE00FFFFF Cortex-M3 PPB Registers, including NVIC, debug, and trace Table 5-5. Peripheral Data Address Map (continued) Address Range Purpose |
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