CY8CKIT-059 datasheet(43/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

Page 42 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

7.2 Universal Digital Block

The Universal Digital Block (UDB) represents an evolutionary

step to the next generation of PSoC embedded digital peripheral

functionality. The architecture in first generation PSoC digital

blocks provides coarse programmability in which a few fixed

functions with a small number of options are available. The new

UDB architecture is the optimal balance between configuration

granularity and efficient implementation. A cornerstone of this

approach is to provide the ability to customize the devices digital

operation to match application requirements.

To achieve this, UDBs consist of a combination of uncommitted

logic (PLD), structured logic (Datapath), and a flexible routing

scheme to provide interconnect between these elements, I/O

connections, and other peripherals. UDB functionality ranges

from simple self contained functions that are implemented in one

UDB, or even a portion of a UDB (unused resources are

available for other functions), to more complex functions that

require multiple UDBs. Examples of basic functions are timers,

counters, CRC generators, PWMs, dead band generators, and

communications functions, such as UARTs, SPI, and I2C. Also,

the PLD blocks and connectivity provide full featured general

purpose programmable logic within the limits of the available

resources.

Figure 7-2. UDB Block Diagram

The main component blocks of the UDB are:



PLD blocks - There are two small PLDs per UDB. These blocks

take inputs from the routing array and form registered or

combinational sum-of-products logic. PLDs are used to

implement state machines, state bits, and combinational logic

equations. PLD configuration is automatically generated from

graphical primitives.



Datapath Module - This 8-bit wide datapath contains structured

logic to implement a dynamically configurable ALU, a variety

of compare configurations and condition generation. This block

also contains input/output FIFOs, which are the primary parallel

data interface between the CPU/DMA system and the UDB.



Status and Control Module - The primary role of this block is to

provide a way for CPU firmware to interact and synchronize

with UDB operation.



Clock and Reset Module - This block provides the UDB clocks

and reset selection and control.

7.2.1 PLD Module

The primary purpose of the PLD blocks is to implement logic

expressions, state machines, sequencers, look up tables, and

decoders. In the simplest use model, consider the PLD blocks as

a standalone resource onto which general purpose RTL is

synthesized and mapped. The more common and efficient use

model is to create digital functions from a combination of PLD

and datapath blocks, where the PLD implements only the

random logic and state portion of the function while the datapath

(ALU) implements the more structured elements.

Figure 7-3. PLD 12C4 Structure

One 12C4 PLD block is shown in Figure 7-3. This PLD has 12

inputs, which feed across eight product terms. Each product term

(AND function) can be from 1 to 12 inputs wide, and in a given

product term, the true (T) or complement (C) of each input can

be selected. The product terms are summed (OR function) to

create the PLD outputs. A sum can be from 1 to 8 product terms

wide. The 'C' in 12C4 indicates that the width of the OR gate (in

this case 8) is constant across all outputs (rather than variable

as in a 22V10 device). This PLA like structure gives maximum

flexibility and insures that all inputs and outputs are permutable

for ease of allocation by the software tools. There are two 12C4

PLDs in each UDB.

7.2.2 Datapath Module

The datapath contains an 8-bit single cycle ALU, with associated

compare and condition generation logic. This datapath block is

optimized to implement embedded functions, such as timers,

counters, integrators, PWMs, PRS, CRC, shifters and dead band

generators, and many others.

PLD

12C4

(8 PTs)

PLD

12C4

(8 PTs)

Datapath

Clock

and Reset

Control

Routing Channel

Datapath

Chaining

PLD

Chaining

Status and

Control

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

IN11

T C

TTT

AND

Array

MC0

MC1

MC2

OUT0

OUT1

OUT2

OUT3

MC3

Carry In

Carry Out

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