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CY8CKIT-059 数据表(PDF) 58 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 58 Page - Infineon Technologies AG |
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58 / 140 page  Document Number: 001-84932 Rev. *N Page 57 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 8.5 Opamps The CY8C58LP family of devices contain four general purpose opamps. Figure 8-7. Opamp The opamp is uncommitted and can be configured as a gain stage or voltage follower on external or internal signals. See Figure 8-8. In any configuration, the input and output signals can all be connected to the internal global signals and monitored with an ADC, or comparator. The configurations are implemented with switches between the signals and GPIO pins. Figure 8-8. Opamp Configurations The opamp has three speed modes, slow, medium, and fast. The slow mode consumes the least amount of quiescent power and the fast mode consumes the most power. The inputs are able to swing rail-to-rail. The output swing is capable of rail-to-rail operation at low current output, within 50 mV of the rails. When driving high current loads (about 25 mA) the output voltage may only get within 500 mV of the rails. 8.6 Programmable SC/CT Blocks The CY8C58LP family of devices contains four switched capacitor/continuous time (SC/CT) blocks. Each switched capacitor/continuous time block is built around a single rail-to-rail high bandwidth opamp. Switched capacitor is a circuit design technique that uses capacitors plus switches instead of resistors to create analog functions. These circuits work by moving charge between capacitors by opening and closing different switches. Nonoverlapping in phase clock signals control the switches, so that not all switches are ON simultaneously. The PSoC Creator tool offers a user friendly interface, which allows you to easily program the SC/CT blocks. Switch control and clock phase control configuration is done by PSoC Creator so users only need to determine the application use parameters such as gain, amplifier polarity, VREF connection, and so on. The same opamps and block interfaces are also connectable to an array of resistors which allows the construction of a variety of continuous time functions. The opamp and resistor array is programmable to perform various analog functions including Naked Operational Amplifier - Continuous Mode Unity-Gain Buffer - Continuous Mode Programmable Gain Amplifier (PGA) - Continuous Mode Transimpedance Amplifier (TIA) - Continuous Mode Up/Down Mixer - Continuous Mode Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode First Order Analog to Digital Modulator - Switched Cap Mode 8.6.1 Naked Opamp The Naked Opamp presents both inputs and the output for connection to internal or external signals. The opamp has a unity gain bandwidth greater than 6.0 MHz and output drive current up to 650 µA. This is sufficient for buffering internal signals (such as DAC outputs) and driving external loads greater than 7.5 kohms. 8.6.2 Unity Gain The Unity Gain buffer is a Naked Opamp with the output directly connected to the inverting input for a gain of 1.00. It has a -3 dB bandwidth greater than 6.0 MHz. 8.6.3 PGA The PGA amplifies an external or internal signal. The PGA can be configured to operate in inverting mode or noninverting mode. The PGA function may be configured for both positive and negative gains as high as 50 and 49 respectively. The gain is adjusted by changing the values of R1 and R2 as illustrated in Figure 8-9. The schematic in Figure 8-9 shows the configuration and possible resistor settings for the PGA. The gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain case is listed in Table 8-3. Opamp VREF GPIO GPIO = Analog Switch GPIO Analog Global Bus Analog Internal Bus Analog Global Bus Opamp Vout to Pin Vin Vout to GPIO Vp to GPIO b) External Uncommitted Opamp a) Voltage Follower Vout to Pin Vp Vn To Internal Signals c) Internal Uncommitted Opamp Vn to GPIO GPIO Pin Opamp Opamp |
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