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CY8CKIT-059 数据表(PDF) 61 Page - Infineon Technologies AG

部件名 CY8CKIT-059
功能描述  Programmable System-on-Chip (PSoC®)
PDF  140 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

CY8CKIT-059 数据表(HTML) 61 Page - Infineon Technologies AG

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Document Number: 001-84932 Rev. *N
Page 60 of 139
PSoC® 5LP: CY8C58LP Family
Datasheet
8.11 Up/Down Mixer
In continuous time mode, the SC/CT block components are used
to build an up or down mixer. Any mixing application contains an
input signal frequency and a local oscillator frequency. The
polarity of the clock, Fclk, switches the amplifier between
inverting or noninverting gain. The output is the product of the
input and the switching function from the local oscillator, with
frequency components at the local oscillator plus and minus the
signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level
frequency components at odd integer multiples of the local
oscillator frequency. The local oscillator frequency is provided by
the selected clock source for the mixer.
Continuous time up and down mixing works for applications with
input signals and local oscillator frequencies up to 1 MHz.
Figure 8-13. Mixer Configuration
8.12 Sample and Hold
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some
applications
require
multiple
signals
to
be
sampled
simultaneously, such as for power calculations (V and I). PSoC
Creator offers a sample and hold component to support this
function.
Figure 8-14. Sample and Hold Topology
(
Φ1 and Φ2 are opposite phases of a clock)
8.12.1 Down Mixer
The S+H can be used as a mixer to down convert an input signal.
This circuit is a high bandwidth passive sample network that can
sample input signals up to 14 MHz. This sampled value is then
held using the opamp with a maximum clock rate of 4 MHz. The
output frequency is at the difference between the input frequency
and the highest integer multiple of the Local Oscillator that is less
than the input.
8.12.2 First Order Modulator - SC Mode
A first order modulator is constructed by placing the switched
capacitor block in an integrator mode and using a comparator to
provide a 1-bit feedback to the input. Depending on this bit, a
reference voltage is either subtracted or added to the input
signal. The block output is the output of the comparator and not
the integrator in the modulator case. The signal is downshifted
and buffered and then processed by a decimator to make a
delta-sigma converter or a counter to make an incremental
converter. The accuracy of the sampled data from the first-order
modulator is determined from several factors. The main
application for this modulator is for a low frequency ADC with
high
accuracy.
Applications
include
strain
gauges,
thermocouples, precision voltage, and current measurement.
Vref
Vout
0
1
Rmix 0 20 k or 40 k
Rmix 0 20 k or 40 k
sc_clk
sc_clk
Vin
C2 = 1.7 pF
C1 = 850 fF
V i
n
V ref
V out
1
2
C
1
C
2
2
1
1
2
1
2
1
1
2
2
C3
C4
Vref
V ref
Φ
Φ
Φ
Φ
Φ
Φ
Φ
Φ
Φ
Φ
Φ
Φ



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