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CY8CKIT-059 数据表(PDF) 84 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 84 Page - Infineon Technologies AG |
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84 / 140 page  Document Number: 001-84932 Rev. *N Page 83 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-22. USBIO Output High Voltage and Current, GPIO Mode Figure 11-23. USBIO Output Rise and Fall Times, GPIO Mode, VDDD = 3.3 V, 25 pF Load Table 11-14. USBIO AC Specifications[41] Parameter Description Conditions Min Typ Max Units Tdrate Full-speed data rate average bit rate 12 – 0.25% 12 12 + 0.25% MHz Tjr1 Receiver data jitter tolerance to next transition –8 – 8 ns Tjr2 Receiver data jitter tolerance to pair transition –5 – 5 ns Tdj1 Driver differential jitter to next transition –3.5 – 3.5 ns Tdj2 Driver differential jitter to pair transition –4 – 4 ns Tfdeop Source jitter for differential transition to SE0 transition –2 – 5 ns Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differential transition –– 14 ns Fgpio_out GPIO mode output operating frequency 3 V ≤ VDDD ≤ 5.5 V – – 20 MHz VDDD = 1.71 V – – 6 MHz Tr_gpio Rise time, GPIO mode, 10%/90% VDDD VDDD > 3 V, 25 pF load – – 12 ns VDDD = 1.71 V, 25 pF load – – 40 ns Tf_gpio Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load – – 12 ns VDDD = 1.71 V, 25 pF load – – 40 ns Note 41. Based on device characterization (Not production tested). |
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