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CY8CKIT-059 数据表(PDF) 35 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 35 Page - Infineon Technologies AG |
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35 / 140 page ![]() Document Number: 001-84932 Rev. *N Page 34 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-8. GPIO Block Diagram Drive Logic PRT[x]DM0 PRT[x]DR PIN Digital Output Path Digital Input Path PRT[x]SLW LCD Logic & MUX PRT[x]DM1 PRT[x]DM2 PRT[x]LCD_EN PRT[x]LCD_COM_SEG Analog Analog Mux Analog Global Digital System Output 0 1 PRT[x]BYP PRT[x]BIE Bidirectional Control Capsense Global Control Switches Pin Interrupt Signal Digital System Input PRT[x]PS PRT[x]CTL Input Buffer Disable Display Data Interrupt Logic PICU[x]INTTYPE[y] PICU[x]INTSTAT Vddio Vddio Vddio Slew Cntl LCD Bias Bus 5 PRT[x]AMUX PRT[x]AG 1 CAPS[x]CFG1 OE In PRT[x]SYNC_OUT PRT[x]DBL_SYNC_IN PICU[x]INTSTAT Naming Convention ٪xﺶ ﭗ Port Number ٪yﺶ ﭗ Pin Number 0 1 0 1 |
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