CY8CKIT-059 datasheet(69/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

Page 68 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

11.2 Device Level Specifications

Specifications are valid for –40 °C

≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. Unless otherwise specified, all charts and graphs show typical values.

Notes

17. The power supplies can be brought up in any sequence. However, once stable, VDDA must be greater than or equal to all other supplies.

18. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin ≤ VDDIO ≤ VDDA.

19. Guaranteed by design, not production tested.

20. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC

Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system

from the device datasheet and component datasheets.

21. Based on device characterization (Not production tested).

Table 11-2. DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

VDDA

Analog supply voltage and input to analog core regulator Analog core regulator enabled

1.8

–

5.5

VDDA

Analog supply voltage, analog regulator bypassed

Analog core regulator disabled

1.71

1.8

1.89

VDDD

Digital supply voltage relative to VSSD

Digital core regulator enabled

1.8

–

VDDA[17]

––

VDDA + 0.1[19]

VDDD

Digital supply voltage, digital regulator bypassed

Digital core regulator disabled

1.71

1.8

1.89

VDDIO[18]

I/O supply voltage relative to VSSIO

1.71

–

VDDA[17]

––

VDDA + 0.1[19]

VCCA

Direct analog core voltage input (Analog regulator

bypass)

Analog core regulator disabled

1.71

1.8

1.89

VCCD

Direct digital core voltage input (Digital regulator bypass) Digital core regulator disabled

1.71

1.8

1.89

IDD[20]

Active Mode

Sum of digital and analog IDDD + IDDA. IDDIOX for I/Os not

included. IMO enabled, bus clock and CPU clock

enabled. CPU executing complex program from flash.

VDDX = 2.7 V to 5.5 V;

FCPU = 3 MHz[21]

T = –40 °C

–

1.9

3.8

T = 25 °C

–

1.9

3.8

T = 85 °C

–

3.8

T = 105 °C

–

3.8

VDDX = 2.7 V to 5.5 V;

FCPU = 6 MHz

T = –40 °C

–

3.1

T = 25 °C

–

3.1

T = 85 °C

–

3.2

T = 105 °C

–

3.2

VDDX = 2.7 V to 5.5 V;

FCPU = 12 MHz[21]

T = –40 °C

–

5.4

T = 25 °C

–

5.4

T = 85 °C

–

5.6

T = 105 °C

–

5.6

VDDX = 2.7 V to 5.5 V;

FCPU = 24 MHz[21]

T = –40 °C

–

8.9

10.5

T = 25 °C

–

8.9

10.5

T = 85 °C

–

9.1

10.5

T = 105 °C

–

9.1

10.5

VDDX = 2.7 V to 5.5 V;

FCPU = 48 MHz[21]

T = –40 °C

–

15.5

T = 25 °C

–

15.4

T = 85 °C

–

15.7

T = 105 °C

–

15.7

17.25

VDDX = 2.7 V to 5.5 V;

FCPU = 62 MHz

T = –40 °C

–

19.5

T = 25 °C

–

19.5

T = 85 °C

–

18.5

19.5

T = 105 °C

–

VDDX = 2.7 V to 5.5 V;

FCPU = 74 MHz

T = –40 °C

–

26.5

T = 25 °C

–

26.5

T = 85 °C

–

T = 105 °C

–

VDDX = 2.7 V to 5.5 V;

FCPU = 80 MHz, IMO

= 3 MHz with PLL

T = –40 °C

–

25.5

T = 25 °C

–

25.5

T = 85 °C

–

22.5

25.5

T = 105 °C

–

22.5

25.5

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