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CY8CKIT-059 数据表(PDF) 36 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 36 Page - Infineon Technologies AG |
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36 / 140 page  Document Number: 001-84932 Rev. *N Page 35 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-9. SIO Input/Output Block Diagram Figure 6-10. USBIO Block Diagram Drive Logic PRT[x]DM0 PRT[x]DR PIN Digital Output Path Digital Input Path PRT[x]SLW PRT[x]DM1 PRT[x]DM2 Digital System Output 0 1 PRT[x]BYP PRT[x]BIE Bidirectional Control Pin Interrupt Signal Digital System Input PRT[x]PS Input Buffer Disable Interrupt Logic PICU[x]INTTYPE[y] PICU[x]INTSTAT Slew Cntl OE In PRT[x]SYNC_OUT PRT[x]DBL_SYNC_IN PICU[x]INTSTAT PRT[x]SIO_DIFF Buffer Thresholds Driver Vhigh PRT[x]SIO_CFG PRT[x]SIO_HYST_EN Naming Convention ‘x’ = Port Number ‘y’ = Pin Number Reference Level Reference Level Drive Logic PRT[15]DR1[7,6] PIN Digital Output Path Digital Input Path Digital System Output 0 1 PRT[15]BYP Pin Interrupt Signal Digital System Input USBIO_CR1[0,1] Interrupt Logic PICU[15]INTTYPE[y] PICU[15]INTSTAT In PRT[15]DBL_SYNC_IN PICU[15]INTSTAT Naming Convention ٪٪ yﺶ ﭗ Pin Number Vddd Vddd Vddd 5 k 1.5 k D+ pin only PRT[15]DM1[6] USBIO_CR1[5] USB or I/O D+ 1.5 k D+ 5 k D+ Open Drain PRT[15]SYNC_OUT USB SIE Control for USB Mode USB Receiver Circuitry Vddd PRT[15]PS[6,7] USBIO_CR1[2] D- 5 k PRT[15]DM1[7] D- Open Drain PRT[15]DM0[6] PRT[15]DM0[7] |
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