CY8CKIT-059 datasheet(53/140 Pages) INFINEON

53 / 140 page

Document Number: 001-84932 Rev. *N

Page 52 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

Figure 8-1. Analog Subsystem Block Diagram

The PSoC Creator software program provides a user friendly

interface to configure the analog connections between the GPIO

and various analog resources and also connections from one

analog resource to another. PSoC Creator also provides

component libraries that allow you to configure the various

analog blocks to perform application specific functions (PGA,

transimpedance amplifier, voltage DAC, current DAC, and so

on). The tool also generates API interface libraries that allow you

to write firmware that allows the communication between the

analog peripheral and CPU/Memory.

8.1 Analog Routing

The PSoC 5LP family of devices has a flexible analog routing

architecture that provides the capability to connect GPIOs and

different analog blocks, and also route signals between different

analog blocks. One of the strong points of this flexible routing

architecture is that it allows dynamic routing of input and output

connections to the different analog blocks.

For information on how to make pin selections for optimal analog

routing, refer to the application note, AN58304 - PSoC® 3 and

PSoC® 5 - Pin Selection for Analog Designs.

8.1.1 Features



Flexible, configurable analog routing architecture



16 analog globals (AG) and two analog mux buses

(AMUXBUS) to connect GPIOs and the analog blocks



Each GPIO is connected to one analog global and one analog

mux bus



Eight analog local buses (abus) to route signals between the

different analog blocks



Multiplexers and switches for input and output selection of the

analog blocks

8.1.2 Functional Description

Analog globals (AGs) and analog mux buses (AMUXBUS)

provide analog connectivity between GPIOs and the various

analog blocks. There are 16 AGs in the PSoC 5LP family. The

analog routing architecture is divided into four quadrants as

shown in Figure 8-2. Each quadrant has four analog globals

(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is

connected to the corresponding AG through an analog switch.

The analog mux bus is a shared routing resource that connects

to every GPIO through an analog switch. There are two

AMUXBUS routes in PSoC 5LP, one in the left half (AMUXBUSL)

and one in the right half (AMUXBUSR), as shown in Figure 8-2.

Analog local buses (abus) are routing resources located within

the analog subsystem and are used to route signals between

different analog blocks. There are eight abus routes in PSoC

5LP, four in the left half (abusl [0:3]) and four in the right half

(abusr [0:3]) as shown in Figure 8-2. Using the abus saves the

analog globals and analog mux buses from being used for

interconnecting the analog blocks.

Multiplexers and switches exist on the various buses to direct

signals into and out of the analog blocks. A multiplexer can have

only one connection on at a time, whereas a switch can have

multiple

connections

simultaneously.

Figure 8-2,

multiplexers are indicated by grayed ovals and switches are

indicated by transparent ovals.

Analog

Interface

SC/CT Block

CMP

CapSense Subsystem

DSI

Array

Clock

Distribution

Decimator

Config&

Status

Registers

PHUB

CPU

Comparators

GPIO

Port

GPIO

Port

DAC

SC/CT Block

SAR

ADC

SAR

ADC

Precision

Reference

CY8CKIT-059 数据表(PDF) 53 Page - Infineon Technologies AG

CY8CKIT-059 数据表(HTML) 53 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载