CY8CKIT-059 datasheet(30/140 Pages) INFINEON

30 / 140 page

Document Number: 001-84932 Rev. *N

Page 29 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

Figure 6-5. Power Mode Transitions

6.2.1.1 Active Mode

Active mode is the primary operating mode of the device. When

in active mode, the active configuration template bits control

which available resources are enabled or disabled. When a

resource is disabled, the digital clocks are gated, analog bias

currents are disabled, and leakage currents are reduced as

appropriate. User firmware can dynamically control subsystem

power by setting and clearing bits in the active configuration

template. The CPU can disable itself, in which case the CPU is

automatically reenabled at the next wakeup event.

When a wakeup event occurs, the global mode is always

returned to active, and the CPU is automatically enabled,

regardless of its template settings. Active mode is the default

global power mode upon boot.

6.2.1.2 Alternate Active Mode

Alternate Active mode is very similar to Active mode. In alternate

active mode, fewer subsystems are enabled, to reduce power

consumption. One possible configuration is to turn off the CPU

and flash, and run peripherals at full speed.

6.2.1.3 Sleep Mode

Sleep mode reduces power consumption when a resume time of

15 µs is acceptable. The wake time is used to ensure that the

regulator outputs are stable enough to directly enter active

mode.

6.2.1.4 Hibernate Mode

In hibernate mode nearly all of the internal functions are

disabled. Internal voltages are reduced to the minimal level to

keep vital systems alive. Configuration state is preserved in

hibernate mode and SRAM memory is retained. GPIOs

configured as digital outputs maintain their previous values and

external GPIO pin interrupt settings are preserved. The device

can only return from hibernate mode in response to an external

I/O interrupt. The resume time from hibernate mode is less than

100 µs.

To achieve an extremely low current, the hibernate regulator has

limited capacity. This limits the frequency of any signal present

on the input pins; no GPIO should toggle at a rate greater than

10 kHz while in hibernate mode. If pins must be toggled at a high

rate while in a low power mode, use sleep mode instead.

6.2.1.5 Wakeup Events

Wakeup events are configurable and can come from an interrupt

or device reset. A wakeup event restores the system to active

mode. Firmware enabled interrupt sources include internally

generated interrupts, power supervisor, central timewheel, and

I/O interrupts. Internal interrupt sources can come from a variety

of peripherals, such as analog comparators and UDBs. The

central timewheel provides periodic interrupts to allow the

system to wake up, poll peripherals, or perform real-time

functions. Reset event sources include the external reset pin

(XRES), WDT, and Precision Reset (PRES).

6.2.2 Boost Converter

Applications that use a supply voltage of less than 1.71 V, such

as solar panels or single cell battery supplies, may use the

on-chip boost converter to generate a minimum of 1.8 V supply

voltage. The boost converter may also be used in any system

that requires a higher operating voltage than the supply provides

such as driving 5.0 V LCD glass in a 3.3 V system. With the

addition of an inductor, Schottky diode, and capacitors, it

produces a selectable output voltage sourcing enough current to

operate the PSoC and other on-board components.

The boost converter accepts an input voltage VBAT from 0.5 V to

3.6 V, and can start up with VBAT as low as 0.5 V. The converter

provides a user configurable output voltage of 1.8 to 5.0 V (VOUT)

in 100 mV increments. VBAT is typically less than VOUT; if VBAT

is greater than or equal to VOUT, then VOUT will be slightly less

than VBAT due to resistive losses in the boost converter. The

block can deliver up to 50 mA (IBOOST) depending on

configuration to both the PSoC device and external components.

The sum of all current sinks in the design including the PSoC

device, PSoC I/O pin loads, and external component loads must

be less than the IBOOST specified maximum current.

Four pins are associated with the boost converter: VBAT, VSSB,

VBOOST, and IND. The boosted output voltage is sensed at the

VBOOST pin and must be connected directly to the chip’s supply

inputs; VDDA, VDDD, and VDDIO if used to power the PSoC

device.

The boost converter requires four components in addition to

those required in a non-boost design, as shown in Figure 6-6 on

page 30. A 22 µF capacitor (CBAT) is required close to the VBAT

pin to provide local bulk storage of the battery voltage and

provide regulator stability. A diode between the battery and VBAT

pin should not be used for reverse polarity protection because

the diodes forward voltage drop reduces the VBAT voltage.

Between the VBAT and IND pins, an inductor of 4.7 µH, 10 µH, or

22 µH is required. The inductor value can be optimized to

increase the boost converter efficiency based on input voltage,

output voltage, temperature, and current. Inductor size is

determined by following the design guidance in this chapter and

electrical specifications. The inductor must be placed within 1 cm

of the VBAT and IND pins and have a minimum saturation current

of 750 mA. Between the IND and VBOOST pins a Schottky diode

must be placed within 1 cm of the pins. The Schottky diode shall

have a forward current rating of at least 1.0 A and a reverse

voltage of at least 20 V. A 22 µF bulk capacitor (CBOOST) must

be connected close to VBOOST to provide regulator output

stability. It is important to sum the total capacitance connected to

the VBOOST pin and ensure the maximum CBOOST specification

is not exceeded. All capacitors must be rated for a minimum of

10 V to minimize capacitive losses due to voltage de-rating.

Active

Manual

Hibernate

Alternate

Active

Sleep

CY8CKIT-059 数据表(PDF) 30 Page - Infineon Technologies AG

CY8CKIT-059 数据表(HTML) 30 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载