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CY8CKIT-059 数据表(PDF) 28 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 28 Page - Infineon Technologies AG |
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28 / 140 page  Document Number: 001-84932 Rev. *N Page 27 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-4. PSoC Power System Notes The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6. You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx pins. You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption. It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a significant percentage of the rated working voltage. VSSB VDDIO0 VSSA VCCA VDDA Digital Regulators Analog Regulator Analog Domain Digital Domain I2C Regulator Sleep Regulator Hibernate Regulator I/O Supply I/O Supply I/O Supply I/O Supply . VDDIO2 VDDIO0 VDDIO3 VDDIO1 0.1 µF 0.1 µF 0.1 µF 0.1 µF VDDD VDDD 1 µF 1 µF VDDA 0.1 µF 0.1 µF 0.1 µF |
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