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CY8CKIT-059 数据表(PDF) 33 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 33 Page - Infineon Technologies AG |
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33 / 140 page  Document Number: 001-84932 Rev. *N Page 32 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-7. Resets The term system reset indicates that the processor as well as analog and digital peripherals and registers are reset. A reset status register shows some of the resets or power voltage monitoring interrupts. The program may examine this register to detect and report certain exception conditions. This register is cleared after a power-on reset. For details see the Technical Reference Manual. 6.3.1 Reset Sources 6.3.1.1 Power Voltage Level Monitors IPOR - Initial Power-on-Reset At initial power on, IPOR monitors the power voltages VDDD, VDDA, VCCD and VCCA. The trip level is not precise. It is set to approximately 1 volt (0.75 V to 1.45 V). This is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. The monitor generates a reset pulse that is at least 150 ns wide. It may be much wider if one or more of the voltages ramps up slowly. After boot, the IPOR circuit is disabled and voltage supervision is handed off to the precise low-voltage reset (PRES) circuit. PRES - Precise Low-Voltage Reset This circuit monitors the outputs of the analog and digital internal regulators after power up. The regulator outputs are compared to a precise reference voltage. The response to a PRES trip is identical to an IPOR reset. In normal operating mode, the program cannot disable the digital PRES circuit. The analog regulator can be disabled, which also disables the analog portion of the PRES. The PRES circuit is disabled automatically during sleep and hibernate modes, with one exception: During sleep mode the regulators are periodically activated (buzzed) to provide supervisory services and to reduce wakeup time. At these times the PRES circuit is also buzzed to allow periodic voltage monitoring. ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when VDDA and VDDD go outside a voltage range. For AHVI, VDDA is compared to a fixed trip level. For ALVI and DLVI, VDDA and VDDD are compared to trip levels that are programmable, as listed in Table 6-5. ALVI and DLVI can also be configured to generate a device reset instead of an interrupt. The monitors are disabled until after IPOR. During sleep mode these circuits are periodically activated (buzzed). If an interrupt occurs during buzzing then the system first enters its wakeup sequence. The interrupt is then recognized and may be serviced. The buzz frequency is adjustable, and should be set to be less than the minimum time that any voltage is expected to be out of range. For details on how to adjust the buzz frequency, see the TRM. 6.3.1.2 Other Reset Sources XRES - External Reset PSoC 5LP has a dedicated XRES pin, which holds the part in reset while held active (low). The response to an XRES is the same as to an IPOR reset. The external reset is active low. It includes an internal pull-up resistor. XRES is active during sleep and hibernate modes. After XRES has been deasserted, at least 10 µs must elapse before it can be reasserted. SRES - Software Reset A reset can be commanded under program control by setting a bit in the software reset register. This is done either directly by the program or indirectly by DMA access. The response to a SRES is the same as after an IPOR reset. Another register bit exists to disable this function. WRES - Watchdog Timer Reset The watchdog reset detects when the software program is no longer being executed correctly. To indicate to the watchdog timer that it is running correctly, the program must periodically reset the timer. If the timer is not reset before a user-specified amount of time, then a reset is generated. Note IPOR disables the watchdog function. The program must enable the watchdog function at an appropriate point in the code by setting a register bit. When this bit is set, it cannot be cleared again except by an IPOR power on reset event. Reset Controller Watchdog Timer External Reset Power Voltage Level Monitors Software Reset Register VDDD VDDA Reset Pin System Reset Processor Interrupt Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt Supply Normal Volt- age Range Available Trip Settings DLVI VDDD 1.71 V-5.5 V 1.70 V-5.45 V in 250 mV increments ALVI VDDA 1.71 V-5.5 V 1.70 V-5.45 V in 250 mV increments AHVI VDDA 1.71 V-5.5 V 5.75 V |
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