CY8CKIT-059 datasheet(45/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

Page 44 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

7.2.2.3 Conditionals

Each datapath has two compares, with bit masking options.

Compare operands include the two accumulators and the two

data registers in a variety of configurations. Other conditions

include zero detect, all ones detect, and overflow. These

conditions are the primary datapath outputs, a selection of which

can be driven out to the UDB routing matrix. Conditional

computation can use the built in chaining to neighboring UDBs

to operate on wider data widths without the need to use routing

resources.

7.2.2.4 Variable MSB

The most significant bit of an arithmetic and shift function can be

programmatically specified. This supports variable width CRC

and PRS functions, and in conjunction with ALU output masking,

can implement arbitrary width timers, counters and shift blocks.

7.2.2.5 Built-in CRC/PRS

The datapath has built in support for single cycle Cyclic

Redundancy Check (CRC) computation and Pseudo Random

Sequence (PRS) generation of arbitrary width and arbitrary

polynomial. CRC/PRS functions longer than 8 bits may be

implemented in conjunction with PLD logic, or built in chaining

may be use to extend the function into neighboring UDBs.

7.2.2.6 Input/Output FIFOs

Each datapath contains two four-byte deep FIFOs, which can be

independently configured as an input buffer (system bus writes

to the FIFO, datapath internal reads the FIFO), or an output

buffer (datapath internal writes to the FIFO, the system bus reads

from the FIFO). The FIFOs generate status that are selectable

as datapath outputs and can therefore be driven to the routing,

to interact with sequencers, interrupts, or DMA.

Figure 7-5. Example FIFO Configurations

7.2.2.7 Chaining

The datapath can be configured to chain conditions and signals

such as carries and shift data with neighboring datapaths to

create higher precision arithmetic, shift, CRC/PRS functions.

7.2.2.8 Time Multiplexing

In applications that are over sampled, or do not need high clock

rates, the single ALU block in the datapath can be efficiently

shared with two sets of registers and condition generators. Carry

and shift out data from the ALU are registered and can be

selected as inputs in subsequent cycles. This provides support

for 16-bit functions in one (8-bit) datapath.

7.2.2.9 Datapath I/O

There are six inputs and six outputs that connect the datapath to

the routing matrix. Inputs from the routing provide the

configuration for the datapath operation to perform in each cycle,

and the serial data inputs. Inputs can be routed from other UDB

blocks, other device peripherals, device I/O pins, and so on. The

outputs to the routing can be selected from the generated

conditions, and the serial data outputs. Outputs can be routed to

other UDB blocks, device peripherals, interrupt and DMA

controller, I/O pins, and so on.

7.2.3 Status and Control Module

The primary purpose of this circuitry is to coordinate CPU

firmware interaction with internal UDB operation.

Figure 7-6. Status and Control Registers

The bits of the control register, which may be written to by the

system bus, are used to drive into the routing matrix, and thus

provide firmware with the opportunity to control the state of UDB

processing. The status register is read-only and it allows internal

UDB state to be read out onto the system bus directly from

internal routing. This allows firmware to monitor the state of UDB

processing. Each bit of these registers has programmable

connections to the routing matrix and routing connections are

made depending on the requirements of the application.

7.2.3.1 Usage Examples

As an example of control input, a bit in the control register can

be allocated as a function enable bit. There are multiple ways to

enable a function. In one method the control bit output would be

routed to the clock control block in one or more UDBs and serve

as a clock enable for the selected UDB blocks. A status example

is a case where a PLD or datapath block generated a condition,

such as a “compare true” condition that is captured and latched

by the status register and then read (and cleared) by CPU

firmware.

7.2.3.2 Clock Generation

Each subcomponent block of a UDB including the two PLDs, the

datapath, and Status and Control, has a clock selection and

control block. This promotes a fine granularity with respect to

allocating clocking resources to UDB component blocks and

allows unused UDB resources to be used by other functions for

maximum system efficiency.

System Bus

A0/A1/ALU

D0/D1

A0/A1/ALU

System Bus

A0/A1/ALU

System Bus

TX/RX

Dual Capture

Dual Buffer

Routing Channel

8-bit Status Register

(Read Only)

8-bit Control Register

(Write/Read)

System Bus

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