CY8CKIT-059 datasheet(72/140 Pages) INFINEON

72 / 140 page

Document Number: 001-84932 Rev. *N

Page 71 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

11.3 Power Regulators

Specifications are valid for –40 °C

≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.3.1 Digital Core Regulator

Figure 11-5. Analog and Digital Regulators, VCC vs VDD,

10 mA Load

Figure 11-6. Digital Regulator PSRR vs Frequency and VDD

Table 11-3. AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

FCPU

CPU frequency

1.71 V

≤ VDDD ≤ 5.5 V

–

80.01

MHz

FBUSCLK

Bus frequency

1.71 V

≤ VDDD ≤ 5.5 V

–

80.01

MHz

SVDD[28]

VDD ramp rate

–

0.066

V/µs

TIO_INIT[28]

Time from VDDD/VDDA/VCCD/VCCA ≥ IPOR to

I/O ports set to their reset states

–

µs

TSTARTUP[28]

Time from VDDD/VDDA/VCCD/VCCA ≥ PRES

to CPU executing code at reset vector

VCCA/VDDA = regulated from

VDDA/VDDD, no PLL used, fast IMO

boot mode (48 MHz typ.)

–

µs

VCCA/VCCD = regulated from

VDDA/VDDD, no PLL used, slow IMO

boot mode (12 MHz typ.)

–

µs

TSLEEP[28]

Wakeup from sleep mode –

Application of non-LVD interrupt to beginning

of execution of next CPU instruction

–

µs

THIBERNATE[28] Wakeup from hibernate mode – Application

of external interrupt to beginning of

execution of next CPU instruction

–

150

µs

Note

28. Based on device characterization (Not production tested).

Table 11-4. Digital Core Regulator DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

VDDD

Input voltage

1.8

–

5.5

VCCD

Output voltage

–

1.80

–

Regulator output capacitor

±10%, X5R ceramic or better. The two VCCD

pins must be shorted together, with as short

a trace as possible, see “Power System”

section on page 26

0.9

1.1

µF

100

0.1

100

1000

Frequency, kHz

Vdd=4.5V

Vdd=3.6V

Vdd=2.7V

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