CY8CKIT-059 datasheet(20/140 Pages) INFINEON

20 / 140 page

Document Number: 001-84932 Rev. *N

Page 19 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

5. Memory

5.1 Static RAM

CY8C58LP static RAM (SRAM) is used for temporary data

storage. Code can be executed at full speed from the portion of

SRAM that is located in the code space. This process is slower

from SRAM above 0x20000000. The device provides up to 64

KB of SRAM. The CPU or the DMA controller can access all of

SRAM. The SRAM can be accessed simultaneously by the

Cortex-M3 CPU and the DMA controller if accessing different

32-KB blocks.

5.2 Flash Program Memory

Flash memory in PSoC devices provides nonvolatile storage for

user firmware, user configuration data, bulk data storage, and

optional ECC data. The main flash memory area contains up to

256 KB of user program space.

Up to an additional 32 KB of flash space is available for Error

Correcting Codes (ECC). If ECC is not used this space can store

device configuration data and bulk user data. User code may not

be run out of the ECC flash memory section. ECC can correct

one bit error and detect two bit errors per 8 bytes of firmware

memory; an interrupt can be generated when an error is

detected. The flash output is 9 bytes wide with 8 bytes of data

and 1 byte of ECC data.

The CPU or DMA controller read both user code and bulk data

located in flash through the cache controller. This provides

higher CPU performance. If ECC is enabled, the cache controller

also performs error checking and correction.

Flash programming is performed through a special interface and

preempts code execution out of flash. Code execution may be

done out of SRAM during flash programming.

The flash 24programming interface performs flash erasing,

programming and setting code protection levels. Flash in-system

serial programming (ISSP), typically used for production

programming, is possible through both the SWD and JTAG

interfaces.

In-system

programming,

typically

used

for

bootloaders, is also possible using serial interfaces such as I2C,

USB, UART, and SPI, or any communications protocol.

5.3 Flash Security

All PSoC devices include a flexible flash protection model that

prevents access and visibility to on-chip flash memory. This

prevents duplication or reverse engineering of proprietary code.

Flash memory is organized in blocks, where each block contains

256 bytes of program or data and 32 bytes of ECC or

configuration data.

The device offers the ability to assign one of four protection

levels to each row of flash. Table 5-1 lists the protection modes

available. Flash protection levels can only be changed by

performing a complete flash erase. The Full Protection and Field

Upgrade settings disable external access (through a debugging

tool such as PSoC Creator, for example). If your application

requires code update through a boot loader, then use the Field

Upgrade setting. Use the Unprotected setting only when no

security is needed in your application. The PSoC device also

offers an advanced security feature called Device Security which

permanently disables all test, programming, and debug ports,

protecting your application from external access (see the

“Device Security” section on page 64). For more information on

how to take full advantage of the security features in PSoC, see

the PSoC 5 TRM.

Disclaimer

Note the following details of the flash code protection features on

Cypress devices.

Cypress products meet the specifications contained in their

particular Cypress datasheets. Cypress believes that its family

of products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

5.4 EEPROM

PSoC EEPROM memory is a byte addressable nonvolatile

memory. The CY8C58LP has 2 KB of EEPROM memory to store

user data. Reads from EEPROM are random access at the byte

level. Reads are done directly; writes are done by sending write

commands to an EEPROM programming interface. CPU code

execution can continue from flash during EEPROM writes.

EEPROM is erasable and writeable at the row level. The

EEPROM is divided into 128 rows of 16 bytes each. The factory

default values of all EEPROM bytes are 0.

Because the EEPROM is mapped to the Cortex-M3 Peripheral

region, the CPU cannot execute out of EEPROM. There is no

ECC hardware associated with EEPROM. If ECC is required it

must be handled in firmware.

It can take as much as 20 milliseconds to write to EEPROM or

flash. During this time the device should not be reset, or

unexpected changes may be made to portions of EEPROM or

flash. Reset sources (see Reset Sources on page 32) include

XRES pin, software reset, and watchdog; care should be taken

to make sure that these are not inadvertently activated. In

addition, the low voltage detect circuits should be configured to

generate an interrupt instead of a reset.

Table 5-1. Flash Protection

Protection

Setting

Allowed

Not Allowed

Unprotected

External read and write

+ internal read and write

–

Factory

Upgrade

External write + internal

read and write

External read

Field Upgrade Internal read and write

External read and

write

Full Protection Internal read

External read and

write + internal write

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