CY8CKIT-059 datasheet(40/140 Pages) INFINEON

40 / 140 page

Document Number: 001-84932 Rev. *N

Page 39 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

6.4.13 SIO as Comparator

This section applies only to SIO pins. The adjustable input level

feature of the SIOs as explained in the Adjustable Input Level on

page 38 can be used to construct a comparator. The threshold

for the comparator is provided by the SIO's reference generator.

The reference generator has the option to set the analog signal

routed through the analog global line as threshold for the

comparator. Note that a pair of SIO pins share the same

threshold.

The digital input path in Figure 6-9 on page 35 illustrates this

functionality. In the figure, ‘Reference level’ is the analog signal

routed through the analog global. The hysteresis feature can

also be enabled for the input buffer of the SIO, which increases

noise immunity for the comparator.

6.4.14 Hot Swap

This section applies only to SIO pins. SIO pins support ‘hot swap’

capability to plug into an application without loading the signals

that are connected to the SIO pins even when no power is

applied to the PSoC device. This allows the unpowered PSoC to

maintain a high impedance load to the external device while also

preventing the PSoC from being powered through a SIO pin’s

protection diode.

Powering the device up or down while connected to an

operational I2C bus may cause transient states on the SIO pins.

The overall I2C bus design should take this into account.

6.4.15 Overvoltage Tolerance

All I/O pins provide an overvoltage tolerance feature at any

operating VDD.



There are no current limitations for the SIO pins as they present

a high impedance load to the external circuit.



The GPIO pins must be limited to 100 µA using a current limiting

resistor. GPIO pins clamp the pin voltage to approximately one

diode above the VDDIO supply.



In case of a GPIO pin configured for analog input/output, the

analog voltage on the pin must not exceed the VDDIO supply

voltage to which the GPIO belongs.

A common application for this feature is connection to a bus such

as I2C where different devices are running from different supply

voltages. In the I2C case, the PSoC chip is configured into the

Open Drain, Drives Low mode for the SIO pin. This allows an

external pull-up to pull the I2C bus voltage above the PSoC pin

supply. For example, the PSoC chip could operate at 1.8 V, and

an external device could run from 5 V. Note that the SIO pin’s

VIH and VIL levels are determined by the associated VDDIO

supply pin.

The SIO pin must be in one of the following modes: 0 (high

impedance analog), 1 (high impedance digital), or 4 (open drain

drives low). See Figure 6-11 for details. Absolute maximum

ratings for the device must be observed for all I/O pins.

6.4.16 Reset Configuration

While reset is active all I/Os are reset to and held in the High

Impedance Analog state. After reset is released, the state can

be reprogrammed on a port-by-port basis to pull-down or pull-up.

To ensure correct reset operation, the port reset configuration

data is stored in special nonvolatile registers. The stored reset

data is automatically transferred to the port reset configuration

registers at reset release.

6.4.17 Low Power Functionality

In all low power modes the I/O pins retain their state until the part

is awakened and changed or reset. To awaken the part, use a

pin interrupt, because the port interrupt logic continues to

function in all low power modes.

6.4.18 Special Pin Functionality

Some pins on the device include additional special functionality

in addition to their GPIO or SIO functionality. The specific special

function pins are listed in “Pinouts” on page 6. The special

features are:



Digital



4- to 25-MHz crystal oscillator



32.768-kHz crystal oscillator



Wake from sleep on I2C address match. Any pin can be used

for I2C if wake from sleep is not required.



JTAG interface pins



SWD interface pins



SWV interface pins



TRACEPORT interface pins



External reset



Analog



Opamp inputs and outputs



High current IDAC outputs



External reference inputs

6.4.19 JTAG Boundary Scan

The device supports standard JTAG boundary scan chains on

all pins for board level test.

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