CY8CKIT-059 datasheet(27/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

Page 26 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

6.1.2.2 32.768 kHz ECO

The 32.768-kHz external crystal oscillator (32kHzECO) provides

precision timing with minimal power consumption using an

external 32.768-kHz watch crystal (see Figure 6-3). The

32kHzECO also connects directly to the sleep timer and provides

the source for the RTC. The RTC uses a 1 second interrupt to

implement the RTC functionality in firmware.

The oscillator works in two distinct power modes. This allows

users to trade off power consumption with noise immunity from

neighboring circuits. The GPIO pins connected to the external

crystal and capacitors are fixed.

Figure 6-3. 32kHzECO Block Diagram

It is recommended that the external 32.768-kHz watch crystal

have a load capacitance (CL) of 6 pF or 12.5 pF. Check the

crystal manufacturer's datasheet. The two external capacitors,

CL1 and CL2, are typically of the same value, and their total

capacitance, CL1CL2 / (CL1 + CL2), including pin and trace

capacitance, should equal the crystal CL value. For more infor-

mation, refer to application note AN54439: PSoC 3 and PSoC 5

External Oscillators. See also pin capacitance specifications in

the “GPIO” section on page 76.

6.1.2.3 Digital System Interconnect

The DSI provides routing for clocks taken from external clock

oscillators connected to I/O. The oscillators can also be

generated within the device in the digital system and UDBs.

While the primary DSI clock input provides access to all clocking

resources, up to eight other DSI clocks (internally or externally

generated) may be routed directly to the eight digital clock

dividers. This is only possible if there are multiple precision clock

sources.

6.1.3 Clock Distribution

All seven clock sources are inputs to the central clock distribution

system. The distribution system is designed to create multiple

high precision clocks. These clocks are customized for the

design’s requirements and eliminate the common problems

found with limited resolution prescalers attached to peripherals.

The clock distribution system generates several types of clock

trees.



The system clock is used to select and supply the fastest clock

in the system for general system clock requirements and clock

synchronization of the PSoC device.



Bus clock 16-bit divider uses the system clock to generate the

system’s bus clock used for data transfers and the CPU. The

CPU clock is directly derived from the bus clock.



Eight fully programmable 16-bit clock dividers generate digital

system clocks for general use in the digital system, as

configured by the design’s requirements. Digital system clocks

can generate custom clocks derived from any of the seven

clock sources for any purpose. Examples include baud rate

generators, accurate PWM periods, and timer clocks, and

many others. If more than eight digital clock dividers are

required, the UDBs and fixed function timer/counter/PWMs can

also generate clocks.



Four 16-bit clock dividers generate clocks for the analog system

components that require clocking, such as ADCs and mixers.

The analog clock dividers include skew control to ensure that

critical analog events do not occur simultaneously with digital

switching events. This is done to reduce analog system noise.

Each clock divider consists of an 8-input multiplexer, a 16-bit

clock divider (divide by 2 and higher) that generates ~50% duty

cycle clocks, system clock resynchronization logic, and deglitch

logic. The outputs from each digital clock tree can be routed into

the digital system interconnect and then brought back into the

clock system as an input, allowing clock chaining of up to 32 bits.

6.1.4 USB Clock Domain

The USB clock domain is unique in that it operates largely

asynchronously from the main clock network. The USB logic

contains a synchronous bus interface to the chip, while running

on an asynchronous clock to process USB data. The USB logic

requires a 48-MHz frequency. This frequency can be generated

from different sources, including DSI clock at 48 MHz or doubled

value of 24 MHz from internal oscillator, DSI signal, or crystal

oscillator.

6.2 Power System

The power system consists of separate analog, digital, and I/O

supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It

also includes two internal 1.8 V regulators that provide the digital

(VCCD) and analog (VCCA) supplies for the internal core logic.

The output pins of the regulators (VCCD and VCCA) and the

VDDIO pins must have capacitors connected as shown in

Figure 6-4. The two VCCD pins must be shorted together, with as

short a trace as possible, and connected to a 1 µF ±10% X5R

capacitor. The power system also contains a sleep regulator, an

I2C regulator, and a hibernate regulator.

(Pin P15[2])

32 kHz

Crystal Osc

XCLK32K

32 kHz

crystal

Capacitors

External

Components

(Pin P15[3])

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