CY8CKIT-059 datasheet(26/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

Page 25 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

6.1.1 Internal Oscillators

Figure 6-1 shows that there are two internal oscillators. They can

be routed directly or divided. The direct routes may not have a

50% duty cycle. Divided clocks have a 50% duty cycle.

6.1.1.1 Internal Main Oscillator

In most designs the IMO is the only clock source required, due

to its ±1% accuracy. The IMO operates with no external

components and outputs a stable clock. A factory trim for each

frequency range is stored in the device. With the factory trim,

tolerance varies from ±1% at 3 MHz, up to ±7% at 74 MHz. The

IMO, in conjunction with the PLL, allows generation of CPU and

system clocks up to the device's maximum frequency (see USB

Clock Domain on page 26). The IMO provides clock outputs at

3, 6, 12, 24, 48, and 74 MHz.

6.1.1.2 Clock Doubler

The clock doubler outputs a clock at twice the frequency of the

input clock. The doubler works at input frequency of 24 MHz,

providing 48 MHz for the USB. It can be configured to use a clock

from the IMO, MHzECO, or the DSI (external pin).

6.1.1.3 Phase-Locked Loop

The PLL allows low frequency, high accuracy clocks to be

multiplied to higher frequencies. This is a tradeoff between

higher clock frequency and accuracy and, higher power

consumption and increased startup time.

The PLL block provides a mechanism for generating clock

frequencies based upon a variety of input sources. The PLL

outputs clock frequencies in the range of 24 to 80 MHz. Its input

and feedback dividers supply 4032 discrete ratios to create

almost any desired system clock frequency. The accuracy of the

PLL output depends on the accuracy of the PLL input source.

The most common PLL use is to multiply the IMO clock at 3 MHz,

where it is most accurate, to generate the CPU and system

clocks up to the device’s maximum frequency.

The PLL achieves phase lock within 250 µs (verified by bit

setting). It can be configured to use a clock from the IMO,

MHzECO, or DSI (external pin). The PLL clock source can be

used until lock is complete and signaled with a lock bit. The lock

signal can be routed through the DSI to generate an interrupt.

Disable the PLL before entering low power modes.

6.1.1.4 Internal Low-Speed Oscillator

The ILO provides clock frequencies for low power consumption,

including the watchdog timer, and sleep timer. The ILO

generates up to three different clocks: 1 kHz, 33 kHz, and

100 kHz.

The 1-kHz clock (CLK1K) is typically used for a background

‘heartbeat’ timer. This clock inherently lends itself to low power

supervisory operations such as the watchdog timer and long

sleep intervals using the central timewheel (CTW).

The central timewheel is a 1 kHz, free running, 13-bit counter

clocked by the ILO. The central timewheel is always enabled

except in hibernate mode and when the CPU is stopped during

debug on chip mode. It can be used to generate periodic

interrupts for timing purposes or to wake the system from a low

power mode. Firmware can reset the central timewheel.

The central timewheel can be programmed to wake the system

periodically and optionally issue an interrupt. This enables

flexible, periodic wakeups from low power modes or coarse

timing applications. Systems that require accurate timing should

use the RTC capability instead of the central timewheel.

The 100-kHz clock (CLK100K) can be used as a low power

system clock to run the CPU. It can also generate time intervals

using the fast timewheel.

The fast timewheel is a 5-bit counter, clocked by the 100-kHz

clock. It features programmable settings and automatically

resets when the terminal count is reached. An optional interrupt

can be generated each time the terminal count is reached. This

enables flexible, periodic interrupts of the CPU at a higher rate

than is allowed using the central timewheel.

The 33-kHz clock (CLK33K) comes from a divide-by-3 operation

on CLK100K. This output can be used as a reduced accuracy

version of the 32.768-kHz ECO clock with no need for a crystal.

6.1.2 External Oscillators

Figure 6-1 shows that there are two external oscillators. They

can be routed directly or divided. The direct routes may not have

a 50% duty cycle. Divided clocks have a 50% duty cycle.

6.1.2.1 MHz External Crystal Oscillator

The MHzECO provides high frequency, high precision clocking

using an external crystal (see Figure 6-2). It supports a wide

variety of crystal types, in the range of 4 to 25 MHz. When used

in conjunction with the PLL, it can generate CPU and system

clocks up to the device's maximum frequency (see

Phase-Locked Loop on page 25). The GPIO pins connecting to

the external crystal and capacitors are fixed. MHzECO accuracy

depends on the crystal chosen.

Figure 6-2. MHzECO Block Diagram

(Pin P15[0])

4 - 25 MHz

Crystal Osc

XCLK_MHZ

4 – 25 MHz

crystal

Capacitors

External

Components

(Pin P15[1])

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