CY8CKIT-059 datasheet(44/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

Page 43 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

Figure 7-4. Datapath Top Level

7.2.2.1 Working Registers

The datapath contains six primary working registers, which are

accessed by CPU firmware or DMA during normal operation.

7.2.2.2 Dynamic Configuration RAM

Dynamic configuration is the ability to change the datapath

function and internal configuration on a cycle-by-cycle basis,

under sequencer control. This is implemented using the 8-word

x 16-bit configuration RAM, which stores eight unique 16-bit wide

configurations. The address input to this RAM controls the

sequence, and can be routed from any block connected to the

UDB routing matrix, most typically PLD logic, I/O pins, or from

the outputs of this or other datapath blocks.

ALU

The ALU performs eight general purpose functions. They are:



Increment



Decrement



Add



Subtract



Logical AND



Logical OR



Logical XOR



Pass, used to pass a value through the ALU to the shift register,

mask, or another UDB register

Independent of the ALU operation, these functions are available:



Shift left



Shift right



Nibble swap



Bitwise OR mask

ALU

Mask

Shift

Data Registers

Output

Muxes

FIFOs

Accumulators

Output to

Programmable

Routing

Chaining

Parallel Input/Output

(To/From Programmable Routing)

Input from

Programmable

Routing

Input

Muxes

To/From

Datapath

To/From

Datapath

PHUB System Bus

R/W Access to All

Registers

Table 7-1. Working Datapath Registers

Name

Function

Description

A0 and A1 Accumulators

These are sources and sinks for

the ALU and also sources for the

compares.

D0 and D1 Data Registers

These are sources for the ALU

and sources for the compares.

F0 and F1 FIFOs

These are the primary interface

to the system bus. They can be a

data source for the data registers

and accumulators or they can

capture data from the accumu-

lators or ALU. Each FIFO is four

bytes deep.

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