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CY8CKIT-059 数据表(PDF) 18 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 18 Page - Infineon Technologies AG |
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18 / 140 page  Document Number: 001-84932 Rev. *N Page 17 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 4.4 Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5. Bit 0 of each exception vector indicates whether the exception is executed using Arm or Thumb instructions. Because the Cortex-M3 only supports Thumb instructions, this bit must always be 1. The Cortex-M3 non maskable interrupt (NMI) input can be routed to any pin, via the DSI, or disconnected from all pins. See DSI Routing Interface Description on page 45. The Nested Vectored Interrupt Controller (NVIC) handles interrupts from the peripherals, and passes the interrupt vectors to the CPU. It is closely integrated with the CPU for low latency interrupt handling. Features include: 32 interrupts. Multiple sources for each interrupt. Eight priority levels, with dynamic priority control. Priority grouping. This allows selection of preempting and non preempting interrupt levels. Support for tail-chaining, and late arrival, of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. All interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Number Exception Type Priority Exception Table Address Offset Function 0x00 Starting value of R13 / MSP 1 Reset -3 (highest) 0x04 Reset 2 NMI -2 0x08 Non maskable interrupt 3 Hard fault -1 0x0C All classes of fault, when the corresponding fault handler cannot be activated because it is currently disabled or masked 4 MemManage Programmable 0x10 Memory management fault, for example, instruction fetch from a nonexecutable region 5 Bus fault Programmable 0x14 Error response received from the bus system; caused by an instruction prefetch abort or data access error 6 Usage fault Programmable 0x18 Typically caused by invalid instructions or trying to switch to Arm mode 7–10 - - 0x1C–0x28 Reserved 11 SVC Programmable 0x2C System service call via SVC instruction 12 Debug monitor Programmable 0x30 Debug monitor 13 - - 0x34 Reserved 14 PendSV Programmable 0x38 Deferred request for system service 15 SYSTICK Programmable 0x3C System tick timer 16–47 IRQ Programmable 0x40–0x3FC Peripheral interrupt request #0 - #31 |
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