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CY8CKIT-059 数据表(PDF) 136 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 136 Page - Infineon Technologies AG |
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136 / 140 page  Document Number: 001-84932 Rev. *N Page 135 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Document History Page Description Title: PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84932 Revision ECN Submission Date Description of Change ** 3825653 12/07/2012 Datasheet for new CY8C58LP family *A 3897878 02/07/2013 Updated characterization footnotes in Electrical Specifications. Updated conditions for SAR ADC INL and DNL specifications in Table 11-28 Changed number of opamps in Ordering Information Removed Preliminary status Removed references to CAN. Updated INL VIDAC spec. *B 3902085 02/12/2013 Changed Hibernate wakeup time from 125 µs to 200 µs in Table 6-3 and Table 11-3. *C 3917994 01/03/2013 Added Controller Area Network (CAN) content. *D 4114902 09/30/2013 Added information about 1 KB cache in Features. Added warning on reset devices in the EEPROM section. Added DBGEN field in Table 5-3. Deleted statement about repeat start from the I2C section. Removed TSTG spec from Table 11-1 and added a note clarifying the maximum storage temperature range. Updated chip Idd, regulator, opamp, delta-sigma ADC, SAR ADC, IDAC, and VDAC graphs. Added min and max values for the Regulator Output Capacitor parameter. Updated CIN specs in GPIO DC Specifications and SIO DC Specifications. Updated rise and fall time specs in Fast Strong mode in Table 11-9, and deleted related graphs. Added IIB parameter in Opamp DC Specifications Updated Vos spec conditions and changed TCVos max value from 0.55 to 1 in Table 11-20. Updated Voltage Reference Specifications and IMO AC Specifications. Updated FIMO spec (3 MHz). Updated 100-TQFP package diagram. Added Appendix for CSP package (preliminary). *E 4225729 12/20/2013 Added SIO Comparator Specifications. Changed THIBERNATE wakeup spec from 200 to 150 µs. Updated CSP package details and ordering information. Added 80 MHz parts in Table 12-1. *F 4386988 05/22/2014 Updated General Description and Features. Added More Information and PSoC Creator sections. Updated JTAG IDs in Ordering Information. Updated 100-TQFP package diagram. *G 4587100 12/08/2014 Added link to AN72845 in Note 3. Updated interrupt priority numbers in Section 4.4. Updated Section 5.4 to clarify the factory default values of EEPROM. Corrected ECCEN settings in Table 5-3. Updated Section 6.1.1 and Section 6.1.2. Added a note below Figure 6-4. Updated Figure 6-11. Changed ‘Control Store RAM’ to ‘Dynamic Configuration RAM’ in Figure 7-4 and changed Section 7.2.2.2 heading to ‘Dynamic Configuration RAM’. Updated Section 7.8. |
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