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TMS320F2811 数据表(PDF) 34 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 34 Page - Texas Instruments |
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34 / 173 page  Functional Overview 34 April 2001 − Revised July 2007 SPRS174O Table 3−3. Wait States AREA WAIT-STATES COMMENTS M0 and M1 SARAMs 0-wait Fixed Peripheral Frame 0 0-wait Fixed Peripheral Frame 1 0-wait (writes) 2-wait (reads) Fixed Peripheral Frame 2 0-wait (writes) 2-wait (reads) Fixed L0 & L1 SARAMs 0-wait Fixed OTP (or ROM) Programmable, 1-wait minimum Programmed via the Flash registers. 1-wait-state operation is possible at a reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more information. Flash (or ROM) Programmable, 0-wait minimum Programmed via the Flash registers. 0-wait-state operation is possible at reduced CPU frequency. The CSM password locations are hardwired for 16 wait-states. See Section 3.2.6, Flash (F281x Only), for more information. H0 SARAM 0-wait Fixed Boot-ROM 1-wait Fixed XINTF Programmable, 1-wait minimum Programmed via the XINTF registers. Cycles can be extended by external memory or peripheral. 0-wait operation is not possible. 3.2 Brief Descriptions 3.2.1 C28x CPU The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software investment. Additionally, the C28x is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. C28x and TMS320C2000 are trademarks of Texas Instruments. |
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