TMS320F2811 datasheet(9/173 Pages) TI

9 / 173 page

Tables

April 2001 − Revised July 2007

SPRS174O

Table 6−15. HALT Mode Switching Characteristics

111

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Table 6−16. PWM Switching Characteristics

112

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Table 6−17. Timer and Capture Unit Timing Requirements

112

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Table 6−18. External ADC Start-of-Conversion − EVA − Switching Characteristics

113

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Table 6−19. External ADC Start-of-Conversion − EVB − Switching Characteristics

113

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Table 6−20. Interrupt Switching Characteristics

114

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Table 6−21. Interrupt Timing Requirements

114

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Table 6−22. General-Purpose Output Switching Characteristics

115

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Table 6−23. General-Purpose Input Timing Requirements

116

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Table 6−24. SPI Master Mode External Timing (Clock Phase = 0)

117

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Table 6−25. SPI Master Mode External Timing (Clock Phase = 1)

119

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Table 6−26. SPI Slave Mode External Timing (Clock Phase = 0)

121

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Table 6−27. SPI Slave Mode External Timing (Clock Phase = 1)

123

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Table 6−28. Relationship Between Parameters Configured in XTIMING and Duration of Pulse

125

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Table 6−29. XINTF Clock Configurations

127

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Table 6−30. External Memory Interface Read Switching Characteristics

129

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Table 6−31. External Memory Interface Read Timing Requirements

129

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Table 6−32. External Memory Interface Write Switching Characteristics

130

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Table 6−33. External Memory Interface Read Switching Characteristics

(Ready-on-Read, 1 Wait State)

131

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Table 6−34. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)

131

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Table 6−35. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)

131

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Table 6−36. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)

131

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Table 6−37. External Memory Interface Write Switching Characteristics

(Ready-on-Write, 1 Wait State)

134

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Table 6−38. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)

134

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Table 6−39. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)

134

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Table 6−40. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)

138

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Table 6−41. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)

139

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Table 6−42. DC Specifications

141

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Table 6−43. AC Specifications

142

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Table 6−44. ADC Power-Up Delays

143

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Table 6−45. Sequential Sampling Mode Timing

145

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Table 6−46. Simultaneous Sampling Mode Timing

146

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Table 6−47. McBSP Timing Requirements

148

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Table 6−48. McBSP Switching Characteristics

149

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Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)

151

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Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)

151

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Table 6−51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)

152

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Table 6−52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)

152

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Table 6−53. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)

153

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Table 6−54. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)

153

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Table 6−55. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)

154

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Table 6−56. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)

154

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Table 6−57. Flash Parameters at 150-MHz SYSCLKOUT

155

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Table 6−58. Flash/OTP Access Timing

155

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Table 6−59. Minimum Required Flash Wait-States at Different Frequencies (F281x devices)

156

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Table 6−60. ROM Access Timing

157

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Table 6−61. Minimum Required ROM Wait-States at Different Frequencies (C281x devices)

157

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Table 7−1. Thermal Resistance Characteristics for 179-Ball GHH

159

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