TMS320F2811 datasheet(28/173 Pages) TI

28 / 173 page

Functional Overview

April 2001 − Revised July 2007

SPRS174O

Functional Overview

M0 SARAM

1K x 16

CPU-Timer 0

CPU-Timer 1

INT[12:1]

CLKIN

Real-Time JTAG

CPU-Timer 2

Peripheral Bus

C28x CPU

H0 SARAM

× 16

INT14

NMI

INT13

Memory Bus

M1 SARAM

1K x 16

Flash

128K x 16 (F2812)

128K x 16 (F2811)

64K x 16 (F2810)

Boot ROM

× 16

eCAN

SCIA/SCIB

12-Bit ADC

External Interrupt

Control

(XINT1/2/13, XNMI)

EVA/EVB

Memory Bus

OTP(C)

1K x 16

McBSP

System Control

(Oscillator and PLL

Peripheral Clocking

Low-Power

Modes

WatchDog)

FIFO

PIE

(96 interrupts)(A)

SPI

FIFO

TINT0

TINT1

TINT2

Control

Address(19)

Data(16)

External

Interface

(XINTF)(B)

16 Channels

NOTES: A. 45 of the possible 96 interrupts are used on the devices.

B. XINTF is available on the F2812 and C2812 devices only.

C. On C281x devices, the OTP is replaced with a 1K X 16 block of ROM

GPIO Pins

XRS

X1/XCLKIN

XF_XPLLDIS

Protected by the code-security module.

XINT13

L1 SARAM

4K x 16

XNMI

L0 SARAM

4K x 16

ROM

128K x 16 (C2812)

128K x 16 (C2811)

64K x 16 (C2810)

Figure 3−1. Functional Block Diagram

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