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TMS320F2811 数据表(PDF) 14 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 14 Page - Texas Instruments |
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14 / 173 page  Introduction 14 April 2001 − Revised July 2007 SPRS174O 2.3 Pin Assignments Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) package. Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3 shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin. 2.3.1 Terminal Assignments for the GHH Package See Table 2−2 for a description of each terminal’s function(s). 14 12 13 10 11 89 56 34 12 7 XA[14] XF _XPLLDIS VSSAIO ADCINA0 ADCINA4 VDDA2 VDD1 SCIRXDA XA[16] XD[15] TESTSEL XA[11] ADCINB2 VDDAIO ADCLO ADCINA3 ADCINA7 XREADY XA[17] VSS XA[15] VDD XD[14] TRST XZCS6AND7 VSS ADCINB3 ADCINB0 ADCINB1 ADCINA2 VSSA2 VSS1 SCITXDA VDD EMU1 VSS XA[12] XA[10] TDI VDD ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6 XRS XA[18] XINT1 _XBIO VSS EMU0 TDO TMS XA[9] P M L J H K N G E F D C A B ADCREFP XINT2 _ADCSOC AVDD- REFBG AVSS- REFBG ADCREFM ADCINA5 ADC- BGREFIN XHOLD XNMI _XINT13 VDDIO XA[13] C2TRIP XA[8] C1TRIP VSS XMP/MC ADC- RESEXT VSSA1 VDDA1 ADCINB7 C3TRIP XCLKOUT XA[7] TCLKINA TDIRA MDXA MDRA XD[0] VSS XA[0] T2CTRIP/ EVASOC VDDIO VDD VSS XA[6] VDD MCLKRA XD[1] MFSXA XD[2] CAP1 _QEP1 CAP2 _QEP2 CAP3 _QEPI1 XA[5] T1CTRIP _PDPINTA MCLKXA MFSRA XD[3] VDDIO XD[5] XD[13] T1PWM _T1CMP XA[4] T2PWM _T2CMP VSS VSS SPICLKA XD[4] SPISTEA T3PWM _T3CMP VSS C6TRIP TCLKINB X1/ XCLKIN XHOLDA PWM5 VDD VSS PWM6 VDD VSS XD[6] PWM11 XD[7] C5TRIP VDDIO TDIRB XD[10] VDDIO VSS PWM3 PWM4 XD[12] SPISIMOA XA[1] XRD PWM12 CAP4 _QEP3 CAP5 _QEP4 TEST1 XD[9] X2 VSS XA[3] PWM1 SCIRXDB PWM2 SPISOMIA PWM9 XR/W T4PWM _T4CMP C4TRIP VDD3VFL XD[11] XA[2] XWE CANTXA CANRXA VDDIO XZCS0AND1 PWM10 VSS VDD CAP6 _QEPI2 XD[8] VSS VDD T3CTRIP _PDPINTB T4CTRIP/ EVBSOC VDD XZCS2 SCITXDB TCK PWM7 TEST2 PWM8 Figure 2−1. TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA (Bottom View) |
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