TMS320F2811 datasheet(54/173 Pages) TI

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Functional Overview

April 2001 − Revised July 2007

SPRS174O

Table 3−17. Possible PLL Configuration Modes

PLL MODE

REMARKS

SYSCLKOUT

PLL Disabled

Invoked by tying XPLLDIS pin low upon reset. PLL block is completely

disabled. Clock input to the CPU (CLKIN) is directly derived from the clock

signal present at the X1/XCLKIN pin.

XCLKIN

PLL Bypassed

Default PLL configuration upon power-up, if PLL is not disabled. The PLL

itself is bypassed. However, the /2 module in the PLL block divides the clock

input at the X1/XCLKIN pin by two before feeding it to the CPU.

XCLKIN/2

PLL Enabled

Achieved by writing a non-zero value “n” into PLLCR register. The /2 module

in the PLL block now divides the output of the PLL by two before feeding it to

the CPU.

(XCLKIN * n) / 2

3.10

External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:

•

Fundamental mode, parallel resonant

•

CL (load capacitance) = 12 pF

•

CL1 = CL2 = 24 pF

•

Cshunt = 6 pF

•

ESR range = 25 to 40

Ω

3.11

Watchdog Block

The watchdog block on the F281x and C281x is identical to the one used on the 240x devices. The watchdog

module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up

counter has reached its maximum value. To prevent this, the user disables the counter or the software must

periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog

counter. Figure 3−11 shows the various functional blocks within the watchdog module.

TMS320F2811 数据表(PDF) 54 Page - Texas Instruments

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