TMS320F2811 datasheet(99/173 Pages) TI

99 / 173 page

Electrical Specifications

April 2001 − Revised July 2007

SPRS174O

the aid of additional external components) may be used to meet the power sequencing requirement. See

www.spectrumdigital.com for F2812 eZdsp

 schematics and updates.

Table 6−2. Recommended “Low-Dropout Regulators”

SUPPLIER

PART NUMBER

Texas Instruments

TPS767D301

NOTE:

The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V.

VDD_3.3V†

2.5 V

(see Note A)

3.3 V

VDD_1.8V‡

XRS

1.8 V (or

1.9 V)

XRS

> 8

µs

1.5 V

3.3 V

<10 ms

>1 ms

Power-Up Sequence

Power-Down Sequence

1.8 V (or

1.9 V)

† VDD_3.3V −VDDIO, VDD3VFL, VDDAIO, VDDA1, VDDA2, AVDDREFBG

‡ VDD_1.8V −VDD, VDD1

NOTES: A. 1.8-V (or 1.9 V) supply should ramp after the 3.3-V supply reaches at least 2.5 V.

B. Reset (XRS) should remain low until supplies and clocks are stable. See Figure 6−11, Power-on Reset in Microcomputer Mode

(XMP/MC = 0), for minimum requirements.

C. Voltage supervisor or LDO reset control will trip reset (XRS) first when the 3.3-V supply is off regulation. Typically, this occurs

a few milliseconds before the 1.8-V (or 1.9 V) supply reaches 1.5 V.

D. Keeping reset low (XRS) at least 8

µs prior to the 1.8-V (or 1.9 V) supply reaching 1.5 V will keep the flash module in complete

reset before the supplies ramp down.

E. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9 V) supply reaches at least 1 V, this supply should be ramped

as quickly as possible (after the 3.3-V supply reaches at least 2.5 V).

F. Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.

See Note B

See Note D

See Note C

Figure 6−6. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence − Option 2

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