TMS320F2811 datasheet(53/173 Pages) TI

53 / 173 page

Functional Overview

April 2001 − Revised July 2007

SPRS174O

3.8.1

Loss of Input Clock

In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still

issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical

frequency of 1−4 MHz. The PLLCR register should have been written to with a non-zero value for this feature

to work.

Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset

or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing

(i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the

application firmware to detect the input clock failure and initiate necessary shut-down procedure for the

system.

NOTE:

Applications in which the correct CPU operating frequency is absolutely critical must

implement a mechanism by which the DSP will be held in reset, should the input clocks ever

fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the

capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a

periodic basis to prevent it from getting fully charged. Such a circuit would also help in

detecting failure of the VDD3VFL rail.

3.9

PLL-Based Clock Module

The F281x and C281x have an on-chip, PLL-based clock module. This module provides all the necessary

clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control

to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR

cycles.

The PLL-based clock module provides two modes of operation:

•

Crystal-operation

This mode allows the use of an external crystal/resonator to provide the time base to the device.

•

External clock source operation

This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external

clock source input on the X1/XCLKIN pin.

External Clock Signal

(Toggling 0 −VDD)

CL1

(see Note A)

X1/XCLKIN

Crystal

CL2

(see Note A)

(a)

(b)

NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The

resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding

the proper tank component values that will ensure start-up and stability over the entire operating range.

Figure 3−10. Recommended Crystal / Clock Connection

TMS320F2811 数据表(PDF) 53 Page - Texas Instruments

TMS320F2811 数据表(HTML) 53 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载