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TMS320F2811 数据表(PDF) 65 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 65 Page - Texas Instruments |
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65 / 173 page  Peripherals 65 April 2001 − Revised July 2007 SPRS174O 4.2.9 External ADC Start-of-Conversion EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively. 4.3 Enhanced Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4−4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include: • 12-bit ADC core with built-in S/H • Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.) • Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS • 16-channel, MUXed inputs • Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can be programmed to select any 1 of 16 input channels • Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers) • Sixteen result registers (individually addressable) to store conversion values − The digital value of the input analog voltage is derived by: when input ≤ 0 V Digital Value + 0, Digital Value + 4095 Input Analog Voltage * ADCLO 3 Digital Value + 4096 Input Analog Voltage * ADCLO 3 , when 0 V < input < 3 V Digital Value + 4095, when input ≥ 3 V • Multiple triggers as sources for the start-of-conversion (SOC) sequence − S/W − software immediate start − EVA − Event manager A (multiple event sources within EVA) − EVB − Event manager B (multiple event sources within EVB) • Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS • Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize conversions • EVA and EVB triggers can operate independently in dual-sequencer mode • Sample-and-hold (S/H) acquisition time window has separate prescale control The ADC module in the F281x and C281x has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4−4 shows the block diagram of the F281x and C281x ADC module. The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results. |
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