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TMS320F2811 数据表(PDF) 51 Page - Texas Instruments

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部件名 TMS320F2811
功能描述  Digital Signal Processors
PDF  173 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320F2811 数据表(HTML) 51 Page - Texas Instruments

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Functional Overview
51
April 2001 − Revised July 2007
SPRS174O
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3−15.
Table 3−15. PLL, Clocking, Watchdog, and Low-Power Mode Registers†
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Reserved
0x00 7010
0x00 7017
8
Reserved
0x00 7018
1
Reserved
0x00 7019
1
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
LOSPCP
0x00 701B
1
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
PCLKCR
0x00 701C
1
Peripheral Clock Control Register
Reserved
0x00 701D
1
LPMCR0
0x00 701E
1
Low Power Mode Control Register 0
LPMCR1
0x00 701F
1
Low Power Mode Control Register 1
Reserved
0x00 7020
1
PLLCR
0x00 7021
1
PLL Control Register‡
SCSR
0x00 7022
1
System Control & Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
Reserved
0x00 7024
1
WDKEY
0x00 7025
1
Watchdog Reset Key Register
Reserved
0x00 7026
0x00 7028
3
WDCR
0x00 7029
1
Watchdog Control Register
Reserved
0x00 702A
0x00 702F
6
† All of the above registers can only be accessed, by executing the EALLOW instruction.
‡ The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not
reset PLLCR.



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