TMS320F2811 datasheet(35/173 Pages) TI

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Functional Overview

April 2001 − Revised July 2007

SPRS174O

3.2.2

Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and

peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus

and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and

write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single

cycle 32-bit operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to

fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories

attached to the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses

can be summarized as follows:

Highest:

Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)

Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)

Data Reads

Program Reads (Simultaneous program reads and fetches cannot occur on the memory

bus.)

Lowest:

Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)

3.2.3

Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F281x

and C281x adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes

the various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines

and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on

the F281x and C281x. One version only supports 16-bit accesses (called peripheral frame 2) and this retains

compatibility with C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses

(called peripheral frame 1).

3.2.4

Real-Time JTAG and Analysis

The F281x and C281x implement the standard IEEE 1149.1 JTAG interface. Additionally, the F281x and

C281x support real-time mode of operation whereby the contents of memory, peripheral, and register

locations can be modified while the processor is running and executing code and servicing interrupts. The user

can also single step through non-time critical code while enabling time-critical interrupts to be serviced without

interference. The F281x and C281x implement the real-time mode in hardware within the CPU. This is a

unique feature to the F281x and C281x, no software monitor is required. Additionally, special analysis

hardware is provided that allows the user to set hardware breakpoint or data/address watch-points and

generate various user selectable break events when a match occurs.

3.2.5

External Interface (XINTF) (2812 Only)

This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The

chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single

chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with

a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for

extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe

timing enables glueless interface to external memories and peripherals.

TMS320F2811 数据表(PDF) 35 Page - Texas Instruments

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