TMS320F2811 datasheet(21/173 Pages) TI

21 / 173 page

Introduction

April 2001 − Revised July 2007

SPRS174O

Table 2−2. Signal Descriptions† (Continued)

NAME

DESCRIPTION

PU/PD§

I/O/Z‡

PIN NO.

NAME

DESCRIPTION

PU/PD§

I/O/Z‡

128-PINP

176-PINP

179-PING

JTAG (CONTINUED)

EMU0

D11

137

100

I/O/Z

Emulator pin 0. When TRST is driven high, this pin

is used as an interrupt to or from the emulator

system and is defined as input/output through the

JTAG scan. This pin is also used to put the device

into boundary-scan mode. With the EMU0 pin at a

logic-high state and the EMU1 pin at a logic-low

state, a rising edge on the TRST pin would latch

the device into boundary-scan mode.

NOTE: An external pullup resistor is

recommended on this pin. The value of this

resistor should be based on the drive strength of

the debugger pods applicable to the design. A

2.2-k

Ω to 4.7-kΩ resistor is generally adequate.

Since this is application-specific, it is

recommended that each target board be validated

for proper operation of the debugger and the

application.

EMU1

146

105

I/O/Z

Emulator pin 1. When TRST is driven high, this pin

is used as an interrupt to or from the emulator

system and is defined as input/output through the

JTAG scan. This pin is also used to put the device

into boundary-scan mode. With the EMU0 pin at a

logic-high state and the EMU1 pin at a logic-low

state, a rising edge on the TRST pin would latch

the device into boundary-scan mode.

NOTE: An external pullup resistor is

recommended on this pin. The value of this

resistor should be based on the drive strength of

the debugger pods applicable to the design. A

2.2-k

Ω to 4.7-kΩ resistor is generally adequate.

Since this is application-specific, it is

recommended that each target board be validated

for proper operation of the debugger and the

application.

ADC ANALOG INPUT SIGNALS

ADCINA7

167

119

ADCINA6

168

120

ADCINA5

169

121

8-Channel analog inputs for Sample-and-Hold A.

ADCINA4

170

122

8-Channel analog inputs for Sample-and-Hold A.

The ADC pins should not be driven before VDDA1,

ADCINA3

171

123

The ADC pins should not be driven before VDDA1,

VDDA2, andVDDAIO pins have been fully powered up.

ADCINA2

172

124

VDDA2, andVDDAIO pins have been fully powered up.

ADCINA1

173

125

ADCINA0

174

126

† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡ I = Input, O = Output, Z = High impedance

§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled

in boundary scan mode.

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