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TMS320F2811 数据表(PDF) 77 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 77 Page - Texas Instruments |
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77 / 173 page  Peripherals 77 April 2001 − Revised July 2007 SPRS174O Table 4−7. McBSP Register Summary (Continued) NAME ADDRESS 0x00 78xxh TYPE (R/W) RESET VALUE (HEX) DESCRIPTION MULTICHANNEL CONTROL REGISTERS (CONTINUED) RCERE 17 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 18 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 19 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E XCERF 1A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 1B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 1C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 1D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 1E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H FIFO MODE REGISTERS (applicable only in FIFO mode) FIFO Data Registers‡ DRR2 00 R 0x0000 McBSP Data Receive Register 2 − Top of receive FIFO − Read First FIFO pointers will not advance DRR1 01 R 0x0000 McBSP Data Receive Register 1 − Top of receive FIFO − Read Second for FIFO pointers to advance DXR2 02 W 0x0000 McBSP Data Transmit Register 2 − Top of transmit FIFO − Write First FIFO pointers will not advance DXR1 03 W 0x0000 McBSP Data Transmit Register 1 − Top of transmit FIFO − Write Second for FIFO pointers to advance FIFO Control Registers MFFTX 20 R/W 0xA000 McBSP Transmit FIFO Register MFFRX 21 R/W 0x201F McBSP Receive FIFO Register MFFCT 22 R/W 0x0000 McBSP FIFO Control Register MFFINT 23 R/W 0x0000 McBSP FIFO Interrupt Register MFFST 24 R/W 0x0000 McBSP FIFO Status Register † DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode. ‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers. |
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