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TMS320F2811 数据表(PDF) 58 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 58 Page - Texas Instruments |
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58 / 173 page  Peripherals 58 April 2001 − Revised July 2007 SPRS174O In the F281x and C281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4−2. INT1 to INT12 INT14 28x CPU TINT2 TINT0 PIE CPU-TIMER 0 CPU-TIMER 2 (Reserved for DSP/BIOS) INT13 TINT1 CPU-TIMER 1 XINT13 Figure 4−2. CPU-Timer Interrupts Signals and Output Signal (See Notes A and B) The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value in the period register “PRDH:PRD”. The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4−1 are used to configure the timers. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078). |
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