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TMS320F2811 数据表(PDF) 13 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 13 Page - Texas Instruments |
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13 / 173 page ![]() Introduction 13 April 2001 − Revised July 2007 SPRS174O 2.2 Device Summary Table 2−1 provides a summary of each device’s features. Table 2−1. Hardware Features† FEATURE F2810 F2811 F2812 C2810 C2811 C2812 Instruction Cycle (at 150 MHz) 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns Single-Access RAM (SARAM) (16-bit word) 18K 18K 18K 18K 18K 18K 3.3-V On-Chip Flash (16-bit word) 64K 128K 128K — — — On-Chip ROM (16-bit word) — — — 64K 128K 128K Code Security for On-Chip Flash/SARAM/OTP/ROM Yes Yes Yes Yes Yes Yes Boot ROM Yes Yes Yes Yes Yes Yes OTP ROM (1K X 16) Yes Yes Yes Yes‡ Yes‡ Yes‡ External Memory Interface — — Yes — — Yes Event Managers A and B (EVA and EVB) EVA, EVB EVA, EVB EVA, EVB EVA, EVB EVA, EVB EVA, EVB S General-Purpose (GP) Timers 4 4 4 4 4 4 S Compare (CMP)/PWM 16 16 16 16 16 16 S Capture (CAP)/QEP Channels 6/2 6/2 6/2 6/2 6/2 6/2 Watchdog Timer Yes Yes Yes Yes Yes Yes 12-Bit ADC Yes Yes Yes Yes Yes Yes S Channels 16 16 16 16 16 16 32-Bit CPU Timers 3 3 3 3 3 3 SPI Yes Yes Yes Yes Yes Yes SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB CAN Yes Yes Yes Yes Yes Yes McBSP Yes Yes Yes Yes Yes Yes Digital I/O Pins (Shared) 56 56 56 56 56 56 External Interrupts 3 3 3 3 3 3 Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O Packaging 128-pin PBK 128-pin PBK 179-ball GHH and ZHH 176-pin PGF 128-pin PBK 128-pin PBK 179-ball GHH and ZHH 176-pin PGF A: −40 °C to 85 °C Yes Yes Yes Yes Yes Yes Temperature Options S: −40 °C to 125 °C Yes Yes Yes Yes Yes Yes Q: −40 °C to 125 °C Yes Yes PGF only Yes Yes PGF only Product Status§ TMS TMS TMS TMS TMS TMS † The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Silicon Errata (literature number SPRZ193) has been posted on the Texas Instruments (TI) website. It will be updated as needed. ‡ On C281x devices, OTP is replaced by a 1K X 16 block of ROM. § See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages. |
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