TMS320F2811 datasheet(52/173 Pages) TI

52 / 173 page

Functional Overview

April 2001 − Revised July 2007

SPRS174O

3.8

OSC and PLL Block

Figure 3−9 shows the OSC and PLL block on the F281x and C281x.

X1/XCLKIN

On-Chip

Oscillator

(OSC)

PLL

Bypass

XF_XPLLDIS

OSCCLK (PLL Disabled)

Latch

XPLLDIS

XRS

PLL

4-Bit PLL Select

SYSCLKOUT

CLKIN

CPU

4-Bit PLL Select

XCLKIN

PLL Block

Figure 3−9. OSC and PLL Block

The on-chip oscillator circuit enables a crystal to be attached to the F281x and C281x devices using the

X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the

X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD.

The PLLCR bits [3:0] set the clocking ratio.

Table 3−16. PLLCR Register Bit Definitions

BIT(S)

NAME

TYPE

XRS RESET†

DESCRIPTION

15:4

Reserved

R = 0

0:0

3:0

DIV

R/W

0,0,0,0

SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.

Bit Value

SYSCLKOUT

0000

PLL Bypassed

XCLKIN/2

0001

XCLKIN/2

0010

XCLKIN

0011

XCLKIN * 1.5

0100

XCLKIN * 2

0101

XCLKIN * 2.5

0110

XCLKIN * 3

0111

XCLKIN * 3.5

1000

XCLKIN * 4

1001

XCLKIN * 4.5

1010

XCLKIN * 5

1011

Reserved

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

† The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.

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